參數(shù)資料
型號： TP3410J304
英文描述： IC-ISDN TRANSCEIVER
中文描述： 集成電路- ISDN的收發(fā)器
文件頁數(shù)： 4/32頁
文件大?。?/td> 332K
代理商： TP3410J304
Pin Descriptions
(Continued)
PIN DESCRIPTIONS SPECIFIC TO
MICROWIRE MODE ONLY
(MW=1)
(Continued)
Pin
13
Description
Bx
The digital input for B and, if selected, D
channel data to be transmitted to the line;
must be synchronous with BCLK.
The TRI-STATE output for B and, if
selected, D channel data received from
the line; it is synchronous with BCLK.
The Microwire control channel data input.
The Microwire control channel
TRI-STATE output for status information.
When not enabled by CS , this output is
high-impedance.
The Microwire control channel Clock
input, which may be asynchronous with
BCLK.
The Chip Select input, which enables the
Control channel data to be shifted in and
out when pulled low. When high, this pin
inhibits the Control interface.
The Interrupt output, a latched open-drain
output signal which is normally
high-impedance, and goes low to indicate
a change of status of the loop
transmission system. This latch is cleared
when the Status Register is read by the
microprocessor.
When the D-port is enabled this pin is the
digital input for D channel data to be
transmitted to the line clocked by DCLK
or BCLK, see Register CR2. When the
D-port is disabled via CR2, this pin must
be tied to GND.
When the D-port is enabled this pin is the
TRI-STATE output for D channel data to
be received from the line clocked by
DCLK or BCLK, see Register CR2.
When the D-port is enabled, in DSI Slave
or Master mode, this is a 16 kHz clock
CMOS output for D channel data. When
the D-port is disabled or not used, this
pin must be left open-circuit.
11
Br
18
19
CI
CO
17
CCLK
27
CS
26
INT
16
Dx
15
Dr
14
DCLK
PIN DESCRIPTIONS SPECIFIC TO
GCI MODE ONLY (MW=0)
Pin
28
Description
MW
The Microwire/GCI select input, which
must be tied to GND to enable the GCI
mode at the Digital System Interface.
Pin
27
Description
MO
The GCI Master/Slave select input for the
clock direction. Connect this pin low to
select BCLK and FSa as inputs i.e., GCI
Slave; Selection of LT or NT mode must
be made in register CR2. When MO is
connected high, NT Mode is automatically
selected, and BCLK, FSa and FSb are
outputs, i.e., the GCI Master, see Section
8.
The Bit Clock pin, which controls the
shifting of data on the Bx and Br pins, at
a rate of 2 BCLK cycles per data bit.
When GCI Slave mode is selected (see
Digital Interfaces section), BCLK is an
input which may be any multiple of
16 kHz from 512 kHz to 6.144 MHz. It
need not be synchronous with MCLK.
When GCI Master mode is selected, this
pin is a CMOS output clock at 512 kHz or
1.536 MHz, depending on the connection
of the S2/CLS pin. It is synchronous with
the data on Bx and Br.
The digital input for multiplexed B, D and
control data clocked by BCLK at the rate
of 1 data bit per 2 BCLK cycles, and 32
data bits per 8 kHz frame defined by
FSa.
The open-drain n-channel output for
multiplexed B, D and control data clocked
by BCLK at the rate of 1 data bit per 2
BCLK cycles, and 32 data bits per 8 kHz
frame defined by FSa. A pull-up resistor
is required to define the logical 1 state.
In GCI Slave mode (MO connected low),
this pin is the 8 kHz Frame Sync pulse
input, requiring a positive edge to indicate
the start of the GCI slot time for both
transmit and receive data at Bx and Br. In
GCI Master mode, this pin is the 8 kHz
Frame Sync CMOS output pulse.
In GCI Slave mode (MO = 0):
input pins S2, S1 and S0 together
provide a 3-bit binary-coded select port
for the GCI channel number; S2 is the
msb. These pins must be connected
either to V
CC
D or GND to select the
1-of-8 GCI slots which are available if
BCLK
≥
4.096 MHz is used.
In GCI Master mode (MO = 1)
S2/CLS is the GCI Clock Select input.
Connect this pin high to select BCLK =
1.536 MHz; connect CLS low to select
BCLK = 512 kHz. SO/FSb is a Frame
Sync CMOS output pulse which identifies
the B2 channel.
12
BCLK
13
Bx
11
Br
6
FSa
17
19
7
S2/CLS
S1
SO/FSb
PrintDate=1997/07/09 PrintTime=13:37:55 1109 ds009151 Rev. No. 1
Proof
4
www.national.com
4
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TP3410J-304 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP
TP3410J304/NOPB 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
TP3410J304-X 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
TP3410N304 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP
TP3420A 制造商:NSC 制造商全稱:National Semiconductor 功能描述:ISDN S/T Interface Device
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