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參數(shù)資料
| 型號： | TP3410J304 |
| 英文描述： | IC-ISDN TRANSCEIVER |
| 中文描述： | 集成電路- ISDN的收發(fā)器 |
| 文件頁數(shù)： | 13/32頁 |
| 文件大小： | 332K |
| 代理商： | TP3410J304 |
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Functional Description
(Continued)
7.0 MICROWIRE CONTROL PORT (MW = 1)
When Format 1, 2, 3 or 4 is used, control information and
maintenance channel data is written into and read back from
the TP3410 via the Microwire port consisting of the control
clock CCLK; the serial data input, CI, and output, CO; the
Chip Select input, CS and the interrupt output INT . The MW
pin must be tied high to enable this port, and the port may be
used regardless of whether the device is powered up or
down. Figure 13 and Figures 21, 22, 23 show the timing,
which is compatible with the Microwire port on the HPC and
COPs families of microcontrollers, and Table 3 and Table 4
list the control functions and status indicators.
All read and write operations require 2 contiguous bytes. As
shown in Table 3and Table 4 the first byte is the register ad-
dress and the second byte is the data byte. Status Registers
request service under control of the Interrupt Stack, with the
priority order listed in Table 4
To shift data to and from the TP3410, CCLK must be pulsed
high 16 times while CS is low. Data on the CI input is shifted
into the serial input register on the rising edge of each CCLK
pulse; simultaneously, data is shifted out from CO on each
falling edge of CCLK. Bit 7 of byte 1 is shifted first. CS must
return high at the end of the 2nd byte, after which the con-
tents of the input shift register are decoded, and the data is
loaded into the appropriate programmable register. Pulling
CS low also clears the INT pin if it was pulled low; if another
interrupt condition is queued on the Interrupt Stack it can
only pull the INT pin low when CS is high. When CS is high
the CO pin is in the high-impedance state, enabling the CO
pins of many devices to be multiplexed together.
The TP3410 has an enhanced MICROWIRE port such that it
can connect to standard MICROWIRE master devices (such
an NSC’s HPC and COP families) as well as the SCP (serial
control
port)
interface
master
micro-controller family. SCP is supported on devices such as
MC68302 or the MC145488 HDLC.
from
the
Motorola
TP3410 supports two popular formats used in typical termi-
nal equipment applications.
1.
CCLK idling LOW when CS pin is inactive HIGH, pulsing
LOW/HIGH/LOW for 16 clocks, then returning back to
LOW for idle condition. Data is output on CO pin on the
negative edge and data sampled in on the positive edge
of CCLK. This format (shown in Figure 22) is normally
used with NSC’s microcontrollers from the HPC or the
COP8 family.
2.
CCLK idling HIGH when CS pin inactive HIGH, pulsing
HIGH/LOW/HIGH for 17 clocks, then returning back to
HIGH for idle condition. Data is output on CO pin on the
negative edge and data sampled in on the positive edge
of CCLK. This format (shown in Figure 23) is normally
used with other alternate microcontrollers in the industry.
The first 16 clock pulses are the normal low-going
pulses to shift and sample the microwire data.
The 17
th
pulse is generated with software
by toggling the
CCLK clock polarity bit on the SCP port of MC6302 or
MC145488. It is necessary to deactivate the CS pin
(bring it high) while the CCLK is low as shown in Figure
23
8.0 GCI MODE (MW=0)
Selected by tying the MW pin low, the GCI interface is de-
signed for systems in which PCM and control data are mul-
tiplexed together into 4 contiguous bytes per 8 kHz frame.
Furthermore, in Subscriber Line Cards and NT1–2’s (where
the Digital Interface is slaved to external timing) up to 8 GCI
channels may be carried in 1 frame of a GCI multiplex, with
a combined bit rate from 256 kb/s up to 3088 kb/s.
Pin-programmable GCI-channel assignment for 8 GCI chan-
nels is provided.
Note that GCI mode on the TP3410 requires messages in
the Embedded Operations Channel to be processed by a lo-
cal microcontroller. In Line card and TE applications, GCI
mode can be used with a device such as the TP3451 HDLC
DS009151-13
FIGURE 11. D-Port Interface Timing Using BCLK Format 2
DS009151-14
Shown with example of Time-slot Assignment, and FS
a
= FS
b
FIGURE 12. D-Port Interface Timing Using BCLK Format 3
13
www.national.com
PrintDate=1997/07/09 PrintTime=13:38:16 1109 ds009151 Rev. No. 1
Proof
13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3420J | ISDN Line Interface |
| TP3420N | ISDN Line Interface |
| TP3421J | ISDN Line Interface |
| TP3421N | ISDN Line Interface |
| TP3451J | Protocol Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3410J-304 | 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP |
| TP3410J304/NOPB | 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410J304-X | 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410N304 | 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP |
| TP3420A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:ISDN S/T Interface Device |
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