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參數(shù)資料
| 型號： | TP3410J304 |
| 英文描述： | IC-ISDN TRANSCEIVER |
| 中文描述： | 集成電路- ISDN的收發(fā)器 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 332K |
| 代理商： | TP3410J304 |
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Pin Descriptions
(Continued)
PIN DESCRIPTIONS SPECIFIC TO
GCI MODE ONLY (MW=0)
(Continued)
Pin
18
16
ES2
are local input pins. The status of the
pins can be accessed via the RXM56
register bits 5,6 corresponding to ES1,
ES2.
15
LEC
Latched External Control output, which is
the output of a latched bit in the TXM56
Register.
Description
ES1
While in GCI mode, the ES1, ES2 pins
Note 1:
*
Crystal specifications: 15.36 MHz
±
50 ppm parallel resonant;
R
S
≤
20
. Load with 33 pF to GND each side (+7 pF due to pin capacitance).
Functional Description
1.1 Power-On Initialization
When power is first applied, power-on reset circuitry initial-
izes the TP3410 and puts it into the power-down state, in
which all the internal circuits including the Master oscillator
are inactive and in a low power state except for the
Line-Signal Detect circuit; the line outputs Lo+/Lo are in a
high impedance state. All programmable registers and the
Activation Sequence Controller are reset.
All states in the Command Registers initialize as shown in
their respective code tables. The desired modes for all pro-
grammable functions may be selected by writing to these
registers via the control channel (Microwire or Monitor chan-
nel, as appropriate). Microwire is functional regardless of
whether the device is powered up or down, whereas the GCI
channel requires the BCLK to be running.
1.2 Power-Up/Power-Down Control
Before powering up the device, the Configuration Registers
should be programmed with the required modes.
In Microwire mode and GCI Slave mode, the device is pow-
ered up and the MCLK started by writing the PUP command,
as described in the Activation section. In GCI Master mode,
there are 2 methods of powering up the device: the Bx data
input can be pulled low (local power-up command) or the
10 kHz wake-up tone may be received from the far-end.
The power-down state may be re-entered by writing a
Power-down command. In the power-down state, all pro-
grammed register data is retained. Also, if the loop had been
successfully activated and deactivated, the adaptive circuits
are “frozen” and the coefficients in the Digital Signal Proces-
sors are stored to enable rapid reactivation (“warm-start”).
1.3 Reset
A software reset command is provided to enable the clearing
of the Activation sequencer without disconnecting the power
supply to the device, see the Activation section.
2.0 TRANSMISSION SECTION
2.1 Line Coding And Frame Format
For both directions of transmission, 2B1Q coding is used, as
illustrated in Figure 1 This coding rule requires that binary
data bits are grouped in pairs, and each pair is transmitted
as a symbol, the magnitude of which may be 1 out of 4
equally spaced voltage levels (a “Quat”). There is no symbol
value at 0V in this code, the relative quat magnitudes being
±
1 (the “inner” levels) and
±
3 (the “outer” levels). No redun-
dacy is included in this code, and in the limit there is no
bound to the RDS, although scrambling controls the RDS in
a practical sense ( RDS is the Running Digital Sum, which is
the algebraic summation of all symbol values in a transmis-
sion session).
The frame format used in the TP3410 follows the ANSI stan-
dard, shown in Tables 1, 2 Each complete frame consists of
120 quats, with a line bit rate of 80 kq/s, giving a frame du-
ration of 1.5 ms. A 9 quat syncword defines the framing
boundary. Furthermore, a “superframe” consisting of 8
frames is defined in order to provide sub-channels within the
spare bits M1 to M6. Inversion of the syncword defines the
superframe boundary. Prior to transmission, all data, with the
exception
of
the
syncword,
self-synchronizing scrambler to implement the specified
23rd-order polynomial. Descrambling is included in the re-
ceiver.
is
scrambled
using
a
First Bit
(Sign)
1
1
0
0
Second Bit
(Magnitude)
0
1
1
0
Quat
Pulse Amplitude
(Note 2)
+2.5V
+0.83V
0.83V
2.5V
+3
+1
1
3
Note 2:
For isolated pulses into a 135
termination with recommended
transformer interface.
DS009151-25
FIGURE 1. 2B1Q Line-Coding Rule
5
www.national.com
PrintDate=1997/07/09 PrintTime=13:37:59 1109 ds009151 Rev. No. 1
Proof
5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3410J-304 | 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP |
| TP3410J304/NOPB | 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410J304-X | 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410N304 | 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP |
| TP3420A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:ISDN S/T Interface Device |
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