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Preliminary Data Sheet, Rev. 1
October 2000
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
89
Lucent Technologies Inc.
TMUX Functional Description
(continued)
TMUX Receive Path Overview
A detailed drawing of the TMUX receive path is provided in the bottom half of Figure 16, Detailed Block Diagram of
the TMUX on page 94. For the receive path the TMUX implements two serial inputs for both the work and protect
streams of an MSP 1+1 network interface. Synchronous data (SDH/SONET) framers are implemented to frame on
the incoming receive data streams. One or both may be employed depending on system architecture. The incom-
ing traffic is converted from serial to byte wide parallel. The transport overhead bytes of the incoming traffic are
monitored and dropped via the receive path TOAC drop interface. A multiplexer implements the receive MSP 1+1
payload switch and only one of the incoming streams is passed to the downstream processing blocks. The pointer
interpreter passes pointer information to the 1:3 demultiplexer logic and bus control circuitry provides functions
necessary to manage traffic on the telecom bus drop interface which drops traffic from up to three STS-1/TUG-3
paths on the TMUX receive path. The path overhead bytes are monitored by the path overhead monitor and are
dropped via the receive path POAC drop interface.
Receive Line Framer and Transport Overhead Termination
Input receive data is received at the TMUX synchronous data framer from the high-speed line interface block. The
framer performs a multitude of functions including frame alignment (STS-3/STM-1 or STS-1), B1 BIP-8 check, J0
byte monitoring, descrambling, F1 byte monitoring, B2 BIP-8 check, automatic protection switch (APS) and K2
byte monitoring, AIS-L and RDI-L detection, M1 byte REI-L detection, S1 byte sync status monitoring, and receive
transport overhead access channel (RTOAC) drop. The states of the framer as well as all state changes are
reported, and, if not masked, cause an interrupt. The B1 and B2 byte parity check supports bit and block modes.
The TMUX implements internal performance monitor counters. These counters can count up to one second worth
of BIP errors. The counters operate in either a saturation mode such that the maximum value is retained once
reached, or in a rollover mode. These counters should be optimally read (and cleared) at least once per second.
The J0 monitor supports non-framed, SONET-framed, and SDH-framed 16-byte sequences as well as single J0
byte monitoring mode. APS monitoring is performed on bytes K1[7:0] and K2[7:3]. The value of each is stored and
changes are reported. Bits [2:0] of the K2 byte are monitored independently. Line AIS (AIS-L/MS-AIS) and RDI-L/
MS-RDI are monitored separately and changes are reported. This AIS-L/MS-AIS and RDI-L/MS-RDI information is
also sent to the protection device for add drop multiplex (ADM) applications. The M1 byte monitor operates either
in bit or block mode and allows access to the REI-L/MS-REI errored bit count. The S1 byte can be monitored in two
modes: as an entire 8-bit word or as one 4-bit nibble (bits 7 to 4). Continuous N times detection counters are imple-
mented for these monitoring functions. All automatic receive monitoring functions can be configured to provide an
interrupt to the control system, or the device can be operated in a polled mode.
Receive Transport Overhead Monitor and RTOAC Drop
The receive RTOAC provides access to all of the line section overhead bytes. Even or odd parity is calculated over
all bytes. It has a data rate of 5.184 Mbits/s and consists of a clock, data, and an 8 kHz sync pulse. In an alternate
operating mode, the data communication channel bytes D1—D3 or D4—D12 may transmit a serial 192 kbits/s or a
576 kbits/s data stream onto the RTOAC drop channel.
0783(F)
Figure 13. TMUX RTOAC Timing Diagram
rtoac clk
rtoac sync
rtoac data