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Preliminary Data Sheet, Rev. 1
October 2000
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
347
Lucent Technologies Inc.
M13/M23 Mux/Demux Block Functional Description
(continued)
M13/M23 Demultiplexer
(continued)
Output Select Logic
DS2 Output Selection.
The M23 demultiplexer outputs are fed into 7 DS2 output selection logic blocks. This
allows the M13 to output the demultiplexed DS2 signals or insert AIS.
Each selector is identified by a number y that ranges from 1 to 7 and corresponds directly to M13 outputs
M13_DS2DATA[7—1]
. The outgoing DS2 signals are retimed by an associated clock,
M13_DS2CLK[7—1]
. The
edge of the clocks that is used to retime the data is provisionable to either the rising edge (M13_TDS2_EDGE = 1
(Table 295)) or falling edge (M13_TDS2_EDGE = 0).
The output from each selection block is controlled by the values of bits M13_DS2_OUT_IDLEy (Table 285) and
M13_DS2_OUT_AISy (Table 286).
I
Output is held low when M13_DS2_OUT_IDLEy = 1; otherwise the demuxed DS2 signal is output when
M13_DS2_OUT_AISy = 0 and DS2 AIS is output when M13_DS2_OUT_AISy = 1.
The all 1s DS2 AIS signal is also output under all failure conditions at DS3 level which require automatic AIS inser-
tion at DS2 level.
DS1/E1 Output Selection.
The M12 demultiplexer outputs are fed into 28 DS1/E1 output selection logic blocks.
This allows the M13 to output the demultiplexed DS1/E1 (M13_DS1_OUT_AISx = 0 (Table 274)), or insert AIS
(M13_DS1_OUT_AISx = 1). The all 1s AIS signal is also output under all failure conditions at DS3 or DS2 level
which require automatic AIS insertion at DS1/E1 level.
Each selector is identified by a number x that ranges from 1 to 28 and corresponds directly to a block output
M13_DS1DATA[28—1]
. The outgoing DS1 and/or E1 signals are retimed by an associated clock,
M13_DS1CLK[28—1]
. The edge of the clock that is used to retime the data is provisionable to either the rising
edge (M13_TDS1_EDGEx = 1 (Table 273)) or falling edge (M13_TDS1_EDGEx = 0).
Each output selector number, x can be expressed as either 4y – 3, 4y – 2, 4y – 1, or 4y, where y ranges from 1 to
7. For a given y, the 4 selectors in the group output DS1 signals when M13_OUT_TYPEy = 1 (Table 273), or E1
signals when M13_OUT_TYPEy = 0. In either of these modes, the 4 selectors in the group are controlled by the 2-
bit values OUTSELx, where x = 4y – 3, 4y – 2, 4y – 1, and 4y.
When M13_OUT_TYPEy = 0, the output of selector 4y is held low.