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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet, Rev. 1
October 2000
10
Lucent Technologies Inc.
List of Tables
(continued)
Tables
Page
Table 54. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO) ....................................................... 147
Table 55. TMUX_RHS_CTL, Receive High-Speed Control Parameters (R/W) .................................................. 148
Table 56. TMUX_RLS_BITBLK_CTL, Receive Low-Speed Control Parameters (R/W) ..................................... 149
Table 57. TMUX_RLS_MODE_CTL, Receive Low-Speed Control Parameters (R/W) ....................................... 150
Table 58. TMUX_RAISINH_CTL, Receive Low-Speed Control Parameters (R/W) ............................................ 151
Table 59. TMUX_LOSDETCNT, Receive Low-Speed Control Parameters (R/W) .............................................. 152
Table 60. TMUX_CNTD_TOH_[A—B], Continuous N Times Detect Control Parameters (R/W) ........................ 153
Table 61. TMUX_CNTD_POH_[A—B], Continuous N Times Detect Control Parameters (R/W) ........................ 154
Table 62. TMUX_C2EXP[1—2_3], Continuous N Times Detect Control Parameters (R/W) .............................. 155
Table 63. TMUX_RF1MON, Receive Monitor Values (RO) ................................................................................ 155
Table 64. TMUX_RAPSMON, Receive Monitor Values (RO) ............................................................................. 155
Table 65. TMUX_RS1MON, Receive Monitor Values (RO) ................................................................................ 155
Table 66. TMUX_RPOHMON[1—3][A—D], Receive Monitor Values (RO) ......................................................... 156
Table 67. TMUX_TLS_CTL, Transmit Low-Speed Control Parameters (R/W) ................................................... 157
Table 68. TMUX_THS_PORT_CTL, Transmit High-Speed Port Control Parameters (R/W) .............................. 158
Table 69. TMUX_THS_TOH_CTL, Transmit High-Speed Control Parameters (R/W) ........................................ 159
Table 70. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W) .............................. 161
Table 71. TMUX_TLRDI_CTL, Transmit High-Speed Line RDI Control Parameters (R/W) ................................ 167
Table 72. TMUX_TPRDI_CTL, Transmit High-Speed Path RDI Control Parameters (R/W) ............................... 168
Table 73. TMUX_TZ0_INS_VAL, Transmit TOH and POH Insert Values (R/W) ................................................ 168
Table 74. TMUX_TS1_F1_INS_VAL, Transmit TOH and POH Insert Values (R/W) .......................................... 168
Table 75. TMUX_TAPS_INS_VAL, Transmit TOH and POH Insert Values (R/W) ............................................. 169
Table 76. TMUX_TPOH[1—3]_INS_[A—C], Transmit TOH and POH Insert Values (R/W) ............................... 169
Table 77. TMUX_TBERINS_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W) .................. 171
Table 78. TMUX_THS_ERR_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W) ................ 172
Table 79. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) ............................... 173
Table 80. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) ............................ 175
Table 81. TMUX_TFRAMEOFFSET, Transmit High-Speed Offset Control Parameters (R/W) .......................... 176
Table 82. TMUX_SD_CTL[1—6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W) ............................ 177
Table 83. TMUX_SF_CTL[1—6], B1/B2 Signal Fail Set/Clear Control Registers (R/W) ..................................... 178
Table 84. TMUX_B3SD_CTL[1—6], B3 Signal Degrade Set/Clear Control Registers (R/W) ............................. 178
Table 85. TMUX_B3SF_CTL[1—6], B3 Signal Fail Set/Clear Control Registers (R/W) ...................................... 179
Table 86. TMUX_B1ECNT, Receive B1 Error Counts (RO) ................................................................................ 179
Table 87. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Error Counts (RO) ....................... 179
Table 88. TMUX_B3ECNT[1—3], Receive B3 Error Counts (RO) ...................................................................... 180
Table 89. TMUX_M1ECNT_17_16 and TMUX_M1ECNT_15_0, Receive M1 Error Counts (RO) ..................... 180
Table 90. TMUX_G1ECNT[1—3], Receive G1 Error Counts (RO) ..................................................................... 181
Table 91. TMUX_RPTR_INCCNT[1—3], Receive Pointer Increment Count (RO) .............................................. 182
Table 92. TMUX_RPTR_DECCNT[1—3], Receive Pointer Decrement Count (RO) ........................................... 182
Table 93. TMUX_RJ0EXPECTED[1—8], Expected J0 Byte Sequence (R/W) ................................................... 182
Table 94. TMUX_RJ0CAPTURED[1—8], Captured J0 Receive Value (RO) ...................................................... 182
Table 95. TMUX_TJ0VALUE[1—8], J0 Byte Transmit Insert (R/W) .................................................................... 182
Table 96. TMUX_RJ1EXPECTED1_[1—32], Expected J1 Byte Value for Port 1 (R/W) ..................................... 183
Table 97. TMUX_RJ1EXPECTED2_[1—32], Expected J1 Byte Value for Port 2 (R/W) ..................................... 183
Table 98. TMUX_RJ1EXPECTED3_[1—32], Expected J1 Byte Value for Port 3 (R/W) ..................................... 183
Table 99. TMUX_RJ1CAPTURED1_[1—32], Captured J1 Value for STS #1 (RO) ............................................ 183
Table 100. TMUX_RJ1CAPTURED2_[1—32], Captured J1 Value for STS #2 (RO) .......................................... 183
Table 101. TMUX_RJ1CAPTURED3_[1—32], Captured J1 Value for STS #3 (RO) .......................................... 183
Table 102. TMUX_TJ1VALUE_1[1—32], J1 Byte Transmit Insert for STS #1 (R/W) ......................................... 184
Table 103. TMUX_TJ1VALUE_2[1—32], J1 Byte Transmit Insert for STS #2 (R/W) ......................................... 184
Table 104. TMUX_TJ1VALUE_3[1—32], J1 Byte Transmit Insert for STS #3 (R/W) ......................................... 184
Table 105. TMUX Register Map .......................................................................................................................... 185
Table 106. J1 Monitor .......................................................................................................................................... 208