參數(shù)資料
型號(hào)： STP2202ABGA
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320
封裝： BGA-320
文件頁(yè)數(shù)： 85/106頁(yè)
文件大?。?/td> 519K
代理商： STP2202ABGA
8
STP2202ABGA
Dual Processor System Controller
DSC
June 1998
Sun Microsystems, Inc
1. Generates timing for read, write, and refresh.
2. Converts the physical address in the UPA packet into row and column addresses.
3. Maintains refresh timer.
4. Controls loading and unloading of data from the XB1 read and write buffers.
5. Controls the memory switch CBT (FET multiplexer) selects.
PIF forwards memory requests to the MC. MC communicates with the DPS to schedule delivery of data.
The operation of MC and the memory subsystem is described in further detail in the “DSC User’s Manual”
document, Part No. 950-2117-01.
Coherency Controller (CC)
The CC is responsible for maintaining cache coherency at the system level. A copy of each processors tags is
kept in “Dual Tag” RAM that is connected to the CC. The CC checks the Dual tags or “snoops” on all of the
cacheable transactions. From this snoop it can determine the appropriate response. The operation of the
Coherency Controller is further described in the “DSC User’s Manual” document.
EBus Interface (EB)
EB implements an interface to EBus, an asynchronous 8-bit interface controlled by Slavio. Since DSC contains
no data path, all reading and writing of internal registers has to take place via EBus. Since all internal registers
are 32 bits wide, EB has to perform packing and unpacking.
EB is the only block which can be used in both USC and DSC with minimal change.
The EB block implements reset logic.
The EB block contains a number of global registers.
1. SC_Control register for controlling resets and logging reset status.
2. SC_ID register, which contains DSC’s JEDEC ID number, implementation and version numbers, and
the number of UPA ports that this chip supports.
3. Performance counters: SC_Perf_Ctrl, SC_Perf1, and SC_Perf2. These counters can be configured to
count various events for performance analysis.
The global registers are described in further detail in the “DSC User’s Manual” document.
The operation of EB is described in further detail in the “DSC User’s Manual” document.
Performance Monitors
The DSC has a small block that contains logic to monitor performance. Performance registers can be read after
being set up by programming the SC_Perf_Ctrl register. These registers are dened in the “DSC User’s Man-
ual”. These registers are accessed through the EBus.
JTAG Interface
The DSC has a JTAG interface. This interface block is common to the system ASICs and ports the signal set
used for debugging purposes.
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