參數(shù)資料
型號: STP2202ABGA
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320
封裝: BGA-320
文件頁數(shù): 55/106頁
文件大?。?/td> 519K
代理商: STP2202ABGA
52
STP2202ABGA
Dual Processor System Controller
DSC
June 1998
Sun Microsystems, Inc
4. The Bank Select signal is an OR of the individual group bank select signals.
5. The Bank Select signal does not switch for the first few clocks of a cycle to allow more overlap of
DRAM cycles.
6. The RAS signal of write and read cycles is inverted from the programmed value for the first time
interval. This is to allow RAS to drop immediately for read cycles.
7. In most cases write cycles stretch for one or more clock at the first stretch point waiting for data. One
case without stretch cycles is back to back writes. Read followed by write cases have 3 stretch clocks.
CSRs for 83.3 MHz DSC
The optimized set of Memory CSRs for 83.3 MHz DSC is shown below.
These CSR values were used when generating Figure 36. to Figure 44.
CSR values for the 83.5 MHz UPA case
Address
Value (Hex)
Function
80
a0c1 0f18
Mem_Control0
84
29b7 24a5
RAS_Control
88
0000 2d95
CAS_RD_Control
8c
2936 2692
BankSel_Control
90
2d16 249a
XB1_Buffer_Control
94
24cb 6537
CAS_WR_Control
98
14ac 0270
Phase_Level_Control
9c
02c5 19a8
SIMM_Busy_Rd_Control
a0
0602 0d45
Count_Control
a4
a913 2929
Refresh_Control
a8
29b5 2493
Row_Control
b0
0294 a549
SIMM_Busy_Wr_Control
b4
1290 8548
SIMM_Busy_Refr_Control
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