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| 型號： | STP2202ABGA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320 |
| 封裝： | BGA-320 |
| 文件頁數(shù)： | 54/106頁 |
| 文件大小： | 519K |
| 代理商： | STP2202ABGA |
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51
Dual Processor System Controller
DSC
STP2202ABGA
June 1998
Sun Microsystems, Inc
setting up ROW address one clock before the cycle starts, ORing the bank select signal to allow tighter
overlap on different group reads and writes, Ping Pong point controls the next address switch time for both
same and different groups)
Note:
Factors for different group DRAM cycle concatenation:
All the above except the rst because the control signals are separate. Note that the DRAM write signal is
included as a separate signal even though it is not controlled by CSR timers
Programming Different Group Timing:
Programming the different group timing is more complicated than same group, even though the control sig-
nals are separate, because the address bus and data bus are shared. The simplest case for different group
timing is to just use the same group timer values. This of course does not take advantage of the overlapping
cycles the DSC design allows and the performance increase possible with overlapping cycles.
The DSC allows 100% utilization of the DRAM data bus and 50% utilization of the UPA data bus during back
to back reads. The overlapping ROW address special case, as described above, is used to achieve this through-
put. Two clocks of DRAM data oat time and one clock of UPA data oat time are included. The limiting
factor for overlapping reads is simply the DRAM data bus.
For overlapping writes the limiting factor is the DRAM address bus. One clock of overlap is allowed. The
address bus must remain stable for the second CAS until one clock before the end of the rst write. This
implies that a different group write can not start earlier because the second write ROW timer would switch
from the rst write CAS address to the RAS address. This is a design limitation of the DSC because the ROW
address for the next write is not needed for one more clock.
For overlapping different group reads and writes two cases must be examined; read followed by write and
write followed by read. For write followed by read DRAM cycles limiting factor is the DRAM address bus.
This case is actually identical to the same group write to read timing. No optimization is possible because the
address bus is used until one clock before the end of the write cycle. The following read requires one clock of
address setup time before RAS. Again this is the same overlapping ROW address special case, as described
above. The write ping pong point is set at the end of the second CAS, one clock before the end of the cycle, to
allow a same or different group read to start immediately at the end of the write, without a dead clock.
For the read followed by write case the limiting factor is the UPA data bus. One dead clock is necessary
because of the requirement for one clock of oat time between data masters on the UPA bus. However as
described above, two more dead clocks appear and are related to the internal DSC control handshakes and
XB1 scheduling. The dead clocks show up at the rst stretch point of the write cycle and the resulting timing
is the same as for the same group timing. No different group optimization is possible.
Special Programming Rules.
1. All same and different timers are programmed with a value two less that the desired end count.
2. The Ping Pong point is programmed for a value one less than the address switch time desired.
3. The Ping Pong point and the ROW timer (selects between RAS and CAS address) are independent. If
the Ping Pong point is set correctly the ROW timer can still select the wrong address.
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