參數(shù)資料
型號(hào)： STP2202ABGA
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320
封裝： BGA-320
文件頁(yè)數(shù)： 74/106頁(yè)
文件大?。?/td> 519K
代理商： STP2202ABGA
7
Dual Processor System Controller
DSC
STP2202ABGA
June 1998
Sun Microsystems, Inc
FUNCTIONAL BLOCKS
DSC is divided into ve major blocks:
1. Port Interface (PIF)
2. Datapath Scheduler (DPS)
3. Memory Controller (MC)
4. Coherency Controller(CC)
5. EBus Interface (EB)
Their functions are described in further detail in the following sections.
Port Interface (PIF)
The PIF supports two UPA busses. It is responsible for receiving packets, decoding their destinations, and for-
warding packets to the proper destinations. Cached transactions are typically forwarded to the Memory
Controller. Non-cached transactions are typically forwarded to the proper slave.
UPA address bus 0 has three UPA ports. Each Processor and the U2S can act as either a UPA master or a slave.
UPA address bus 1 implements the UPA64S subset only. It supports only a single graphics slave. This bus is
output only, not bidirectional, and DSC is always the master of this bus. In addition, the graphics slave will
only generate and receive truncated PReply and SReply signals.
PIF controls the arbitration on UPA address bus 0. There are three other masters on this bus, the two proces-
sors and U2S. PIF uses a distributed round robin algorithm as described in the “UPA Interconnect
Architecture” document.
PIF also receives all PReplys from UPA clients.
PIF contains four sets of the following registers (one for each UPA port):
1. SC_Port_Config registers.
2. SC_Port_Status registers.
These registers are described in further detail in the “DSC User’s Manual” document. Part No. 950-2117-01
Datapath Scheduler (DPS)
The DPS is responsible for regulating the ow of data throughout the system. It generates the following:
1. BMX commands for XB1 crossbar switch.
2. S_REPLYs for all clients.
3. UPA_DATASTALL signals.
4. UPA_ECCVALID signals.
DPS contains no software visible registers.
Memory Controller (MC)
MC is responsible for controlling the SIMMs. It performs the following functions.
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