參數(shù)資料
型號(hào): STP2202ABGA
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320
封裝: BGA-320
文件頁數(shù): 37/106頁
文件大?。?/td> 519K
代理商: STP2202ABGA
36
STP2202ABGA
Dual Processor System Controller
DSC
June 1998
Sun Microsystems, Inc
Basic Memory Timing
Because the DSC is expected to operate under a wide range of clock frequencies, Memory Controller (MC)
timing is programmable so that memory timing can be optimized for any given frequency. Memory refresh
and access timing have been divided into a number of segments. Memory Control and Status Register 1
(MCSR1) contains seven elds which allow custom tailoring of any particular segment: WPC1, RCD, PC0, CP,
PC1, RP, and RAS. For a detailed description of these elds, refer to the programming model in the “DSC
User’s Manual.”
The timing diagram in Figure 25 shows a generic template for a read or write transaction, how it is broken
down into segments, and the corresponding elds in MCSR1 which control that particular segment. Each
individual segment is programmable to certain values.
Figure 25. Basic Read/Write Timing
1. RCD is the RAS-to-CAS delay.
2. PC0 is the page cycle 0 time.
3. CP is the CAS-precharge time.
4. PC1 is the page cycle 1 time for a read operation.
5. WPC1 is the page cycle 1 time for a write operation.
6. RP is the RAS-precharge time.
Reads use RCD, PC0, CP, PC1, and RP. Writes only use RCD, CP, WPC1, and RP; PC0 is xed.
The Timing in Figure 26 shows a generic template for a refresh operation.
RAS
CAS
RCD
PC0
CP
PC1/WPC1
RP
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