參數(shù)資料
型號: STP2202ABGA
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320
封裝: BGA-320
文件頁數(shù): 1/106頁
文件大?。?/td> 519K
代理商: STP2202ABGA
DATA SHEET
1
STP2202ABGA
DSC
Dual Processor System Controller
DESCRIPTION
The STP2202BGA is the Dual Processor System Controller, also referred to as DSC, used in a low-cost
high-performing two-processor system. DSC’s primary functions are to provide data coherence control,
memory control, datapaths control, ow control, transaction ordering, and address routing. It regulates the
ow of requests and data on the system’s “UPA” interconnect based on dual cache coherent tags for each of
the two processors.
FEATURES
Performs as a centralized system controller.
Implements four ports on two UPA buses; two for the processors, one for the UPA to SBus interface (U2S)
and one for the Fast Frame Buffer (FFB).
Can also be congured with just one processor.
Schedules the crossbar switch and controls the ow on the UPA data buses.
It can support up to sixteen 60ns SPARCstation
20 type DRAM SIMMs, each with capacities of 16MB,
32MB, 64MB, or 128MB. This can support a total 2GB of system memory.
Coordinates interrupt and reset inputs from Reset, Interrupt and Clock (RIC) and distributes them to the
other system components.
Provides an 8-bit EBus interface to allow read/write of the DSC’s internal registers.
Operates at a maximum frequency of 100 MHz (10 ns cycle time).
Includes a JTAG interface for full chip scan during system tests.
Contains a Phase-Locked-Loop (PLL) to remove skew introduced by the internal clock distribution
network.
June 1998
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