參數(shù)資料
型號(hào)： STP2202ABGA
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320
封裝： BGA-320
文件頁(yè)數(shù)： 75/106頁(yè)
文件大小： 519K
代理商： STP2202ABGA
70
STP2202ABGA
Dual Processor System Controller
DSC
June 1998
Sun Microsystems, Inc
MEMORY PEAK PERFORMANCE
The following tables show the peak bandwidths the DRAM memory system is capable of with the nal
released SCR set. Note that these are true instantaneous values taken form logic analyzer traces using two
processors and picking times when the memory was driven to peaks by overlapping requests. Refresh cycles
are completely overlapped and thus are not included in these values. Actual program measured Bcopy statis-
tics will be less.
Cases of different group overlapping read and write and a concurrent refresh in a third group were observed
proving the SIMM group independence of the DSC memory controller.
2 processor Pulsar at 167 MHz 2:1 mode:
2 processor Pulsar at 200 MHz 3:1 mode:
DTAG TIMING DIAGRAMS
The UPA cache coherence protocol is point-to-point write-invalidate. The unit of cache coherence is a block
size of 64 bytes. Coherent read/write transactions transfer data in 64-byte blocks only, using 4 quadwords. In
order to avoid snoop interference with a processor’s cache Dual set of tags (Dtags) is maintained by SC_MP.
The Dtags contain the 4 MOSI cache states (E & M states are merged) and Dtags support direct mapped cache.
A single 18-bit wide SRAM contains the Dtags for both processors. Since the tag and status bits are 15 bits
wide, only one Dtag can be accessed each cycle. It will take two consecutive clock cycles to snoop the Dtags of
both processors. For timing of the Dtag accesses, please see gures below.
The DTAG is running at the same speed as the DSC clock, i.e. UPA clock. Its’ clock input (SNP CLK) is gener-
ated by DSC. Some buffers have been inserted inside the Coherence Controller to position SNP CLK relative
to DSC CLK to match required timing of DTAG SRAM. The SNP CLK should be ahead of the internal DSC
CLK at least 150 ps but not more than 800 ps.
Sustained Peak Bandwidth, 12ns cycle
Transaction
Same group of SIMMs
Different group of SIMMs
Memory Read
533MB/s
667 MB/s
Memory Write
444 MB/s
Bcopy
381 MB/s
427 MB/s
Sustained Peak Bandwidth, 15ns cycle
Transaction
Same group of SIMMs
Different group of SIMMs
Memory Read
474 MB/s
610 MB/s
Memory Write
356 MB/s
Bcopy
328 MB/s
356 MB/s
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