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參數(shù)資料
| 型號(hào)： | STP2202ABGA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320 |
| 封裝： | BGA-320 |
| 文件頁數(shù)： | 40/106頁 |
| 文件大小： | 519K |
| 代理商： | STP2202ABGA |
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39
Dual Processor System Controller
DSC
STP2202ABGA
June 1998
Sun Microsystems, Inc
diately after the UPA request or not. If there is a refresh occurring, then the refresh must nish before the
request starts. If there are other transactions in progress, then there may be some dependencies as to when the
operation can start depending on whether the request is for the same group of SIMMs or if the request is for a
different group of SIMMs.
A question arises as to when cycles actually start and end. This is not an easy question to answer if you can
only look at UPA transactions and DRAM array outputs. If you use the debug pins and output the internal
Start signal in the MC then that denes the actual beginning of a cycle, but there is no reasonable way to doc-
ument all the possibilities of when the DRAM cycle starts by only observing the UPA requests and DRAM
outputs.
Another question arises as to how cancelled reads affect DRAM timing. They really do not affect reads. In the
case of a cancel (due to the cc deciding to provide the data from the other processor’s cache) the read from
memory continues and is simply not used. The case seen in the lab, where the timing appeared to be a func-
tion of cancels was a bug which should be corrected as of this writing.
Notes on the following timing diagrams regarding stretch points, ping pong points and timer information.
1. The address must be asserted until cycle 5. As described in Chapter 4, Programming Model Section
4.3.5, “Memory Controller Registers,” on page 4-45 of the DSC User’s manual. The correct value to
program PPRdCnt would be 5 - 2 = 3 for this behavior.
2. StretchRd: As described in Section 4.3.5, “Memory Controller Registers,” on page 4-45, there are five
cycles before MRB_Ctrl needs to pulse, therefore the correct stretch point is just before the first pulse.
The value which StretchRd needs to be programmed to is 5 - 2 = 3.
3. Regarding the timer values: As an example, we will look at SameBusyRdRd. This value specifies the
earliest time at which the next read to the same group of SIMMs can start. All these values depend on
the specifics of the system clock speed, the DRAM timing information, and the specific way the
waveforms are programmed. There is an initial cycle at the beginning of the read (which the
subsequent read to the same SIMM will also have). The system clock speed is 12 ns per cycle. The
DRAMs are standard 60 ns DRAMs. Therefore tRAS is 60 ns, tRP is 40 ns, and tRC is 110 ns. We have 5
cycles where RAS is low thus satisfying tRAS, we could have RAS high for 4 cycles giving us 48 ns,
thus satisfying tRP, but then tRC is only 108 ns. Therefore, tRP also needs to be 5 cycles. This means that
the earliest the next cycle to the same group can begin is in 10 cycles. As described in Section 4.3.5,
“Memory Controller Registers,” on page 4-45, we subtract two from this and get 8. SameBusy RdRd
needs to be programmed to 8 for the tightest allowable read to read spacing to the same group. When
looking at timer values for different groups, the worst case timing for the address bus and data bus
must be accounted for, to get the tightest spacing for those.
SIMULATED MC TIMING EXAMPLES AND NOTES
This section contains a set of examples that shows both internal and external waveforms. These samples are
extracted from the simulation tool and are used for illustration only. By reviewing the CSR values, the timing
diagrams, and the descriptions, it is hoped that a better understanding of the MC will be obtained.
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