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參數(shù)資料
| 型號(hào)： | STP2202ABGA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320 |
| 封裝： | BGA-320 |
| 文件頁數(shù)： | 39/106頁 |
| 文件大小： | 519K |
| 代理商： | STP2202ABGA |
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38
STP2202ABGA
Dual Processor System Controller
DSC
June 1998
Sun Microsystems, Inc
Fast path timing is only applicable for memory reads issued from the processor. All other memory accesses
use the normal path.
MEMORY ACCESS TIMINGS AND DESIGNER NOTES
This section shows read, write, and refresh timings for the default frequency of 83.3 MHz (12 ns) for accesses
from both CPU and U2S. The main difference between the CPU and U2S accesses is that the CPU resides on a
128 bit wide data bus and U2S resides on a 64 bit wide data bus, so the data transfer timing is different.
The timing diagrams show best case idle timing. Care must be taken in interpreting these diagrams, since the
timings shown here may not match exactly what might be seen during system operation. The reason is that
the movement of data on the UPA busses and the movement of data on the memory bus is somewhat decou-
pled by the read and write buffers in the XB1 chips.
The signals can be divided into two groups. The rst group consists of MEMADDR, RAS_L, CAS_L, WE_L,
MRBCTRL, and MWBCTRL, which are all generated by the Memory Controller. Their timing relationships
are invariant and will match what is shown in these diagrams except for those instances where a stretch might
occur. The stretch points have been indicated. The second group consists of UPA_SREPLY, XB1CMD, and
UPA_DATASTALL, which are all generated by the Datapath Scheduler. Their timing relationships are invari-
ant and will match what is shown in these diagrams. However, the relationships between the two groups are
not invariant; they will vary depending on whether the datapaths and DSC are idle or not, and whether it is a
read or write transaction. The diagrams here only show what happens when everything is completely idle.
A precharge operation is performed between every memory access, regardless of whether the two accesses go
to the same SIMM or to different SIMMs. The DSC MC does not leave SIMMs in page mode, however, it does
overlap successive memory operations going to different SIMMs, hiding some of the precharge time in some
cases. Back to back reads or back to back writes are separated only by the time which the different SIMM
Groups share their common data bus, assuming that the requests can be issued quickly enough at the address
bus. and the MC is not stalled with the Stretch Counter.
The DRAM cycle begins on the rst programmed cycle and ends the cycle after the longest cycle pro-
grammed. For example. if the RAS generator is programmed to last 10 cycles, but the CAS generator is
programmed for 14 cycles, then the DRAM cycle for that SIMM ends on the 15th cycle. The exact point at
which the cycle actually starts is not possible to document. If the system is completely idle, and there are no
refreshes occurring, then the cycle starts the next cycle after the PIF sends it’s request which could be imme-
UPA_ADDRBUS0
MEMADDR[12:0]
RAS
Row Address
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