參數(shù)資料
型號: STP2202ABGA
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320
封裝: BGA-320
文件頁數(shù): 30/106頁
文件大?。?/td> 519K
代理商: STP2202ABGA
3
Dual Processor System Controller
DSC
STP2202ABGA
June 1998
Sun Microsystems, Inc
XB1 (STP2230SOP)
The three port crossbar interconnects a 144-bit (128 + 16 ECC) UPA data bus accessed by two processors, a
72-bit (64 + 8 ECC) UPA data bus accessed by the U2S and the FFB, and a 288-bit wide memory bus. There is
a 2 port switch (CBT) between 288-bit memory bus and 576-bit SIMM data. The crossbar and system memory
access are controlled by the DSC.
Cross Bar Technology Sus Switch (CBT)
The CBT switch is a 2 port switch between a 576 bit memory bus (SIMM side) and a 288 bit data bus (XB1
side). To maintain a manageable pin count, the devices are sliced so that 18 parts are needed to form the com-
plete switch function. The CBT switch part number is: TI SN74CBT16233.
Fast Frame Buffer (FFB)
On-board graphics interfaces with the system through an output only UPA64S graphics port. The FFB is
always the slave, with the DSC the master. UPA Address Bus 1 is used to supply address information, The
UPA I/O Data Bus is the output path for the graphics data.
RIC (STP2210)
The RIC’s main function for the DSC is the import of reset status from system power on, pushbutton, or
keyboard resets.
DTAG
Dual Tag SRAM attached to DSC’s coherency controller, which keeps a copy of each processor’s tags.
Note:
The U2P and UIO could replace the U2S and SlavIO, respectively, if the system utilizes PCI buses.
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