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參數(shù)資料
| 型號(hào)： | STP2202ABGA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320 |
| 封裝： | BGA-320 |
| 文件頁數(shù)： | 43/106頁 |
| 文件大?。?/td> | 519K |
| 代理商： | STP2202ABGA |
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41
Dual Processor System Controller
DSC
STP2202ABGA
June 1998
Sun Microsystems, Inc
Reads to Different Groups
Figure 30 shows consecutive reads from two groups from CPU 1 and then CPU 0. There appears to be some
optimization that can be made here with the Diff_Busy_RD_RD counter. The limiting factors include the
Memory Address and the RB_Busy signal. It may be necessary to move out the StretchTimerRd by two cycles
so that the MC samples RB_Busy at a more appropriate time. Right before you need to start lling the XB1
buffer is the suggested time. This would be a cycle before the internal mrb_ctrl signals are activated. It
appears that the Diff_Busy _RD_RD counter could be reduced by as many as 5 cycles if the StretchTimer Rd is
increased by 2 cycles.
Reads to the Same Group
Figure 31 shows consecutive reads to the same SIMM group. The CAS generator is currently taking 10 cycles.
Since it must be in idle before accepting another start signal, only be reducing the CAS generator state
machine sequence can we reduce the SIMMBusy count. Since the cycle count in the last phase of CAS_RD is
2, the state machine effectively cycles for 2 counts during that stage. Reducing the last phase to 1 will have no
effect on the waveform, yet will let the state machine go to the idle state 1 cycle earlier. Hence, a start pulse can
be received 1 cycle earlier.
Write followed by a read
In this example, shown in Figure 32, a write is followed by a read in the same group. This example shows the
internal Hold0 signal, which keeps the cycles in the timer “timer0Wr” from decrementing. This hold signal is
the result of WB_Busy being active when the StretchTimerWr0 counter has expired and polls WB_Busy to see
if the XB1 buffer has acquired it’s data. The next cycle, XB1 has acquired the data, the DPS sends DM_WBAck
and the WB_Busy goes inactive and allows the timer0Wr counter to proceed.
The limiting factor in starting the Read in this case is the rising edge of CAS. It does not appear that any addi-
tional cycles can be gained from this sequence.
Waveform generators
Figure 33. shows various waveform generator state machine sequences for both a write and a read.
Stretch Write counters
Figure 34. shows the stretch write counters. It a sequence of two writes, one from CPU1 and the next from
U2S. When the stretch write counters expire, they check the WB_Busy signal to see if the XB1 buffer is loaded.
From the gure, we can see that the CPU data is loaded very quickly and there is only 1 hold state before the
both SIMM pairs can be written. However, the second write is from U2S and the waveform generators are
held for both the rst and second datums. The important thing to watch for is that the StretchWr1 must be
long enough so that it samples WB_Busy after the second DM_WBAck arrives. If StretchWr1 is too small, it
will sample WB_Busy during after the rst DM_WBAck and think that data has arrived and inappropriately
write the data to memory. Thankfully, the DPS block will always place DM_WBAck 4 cycles apart on Writes
from U2S and the StrechWr1 counter is held when the hold signal is active.
For performance, it’s best to minimize the StretchWr counters.
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