參數(shù)資料
型號: STP2202ABGA
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320
封裝: BGA-320
文件頁數(shù): 53/106頁
文件大?。?/td> 519K
代理商: STP2202ABGA
50
STP2202ABGA
Dual Processor System Controller
DSC
June 1998
Sun Microsystems, Inc
83.3 MHZ DSC TIMING EXAMPLES AND NOTES
CSR Programming Notes
This section includes empirical knowledge about programming CSRs. Generating a functional CSR set is a
difcult process. Everything has to be perfect for the set to work in actual hardware which makes debug ugly.
There are 384 bits to program, each has an effect on the DRAM waveforms generated, or the DRAM cycle to
cycle timing, or the DRAM to UPA interface. To assist future DSC CSR programmers the following notes are
provided to guide the process and answer some of the difcult questions that came up during generation of
the CSRs presented in this document.
Programming Same Group Timing:
The most important point for programming same group timing is to wait to start the following group until all
the timers from the rst group have nished. No overlapping signals are allowed because reloading a count-
ing timer with a new countdown value is not supported by this design. An example of a failure created by
violating this rule is overlapping a refresh cycle behind a write cycle. If the write CAS timer is not nished
when the refresh cycle starts then the refresh cycle will have CAS high for the entire cycle - a missing CAS
refresh cycle.
A special case that requires overlapping into the previous cycle is a DRAM read cycle. Optimized timing has
ben implemented to allow minimum latency for reads. The DRAM RAS signal is dropped immediately (clock
0) in a read cycle. This requires that the ROW address is available one clock previously. To accomplish this the
Ping Pong point of the previous cycle is used as a switch time to output the next read ROW address. For this
case the Ping Pong point is used for the same group addressing, not just for switching to a different group
address.
Finally the DRAM timing parameters must be met. The DRAM cycle time, RAS and CAS precharge time
between cycles must be met.
For all cases except one the DSC concatenates DRAM cycles based on the minimum value of the timers. That
case is a read followed by write. One dead clock is necessary because of the requirement for one clock of oat
time between data masters on the UPA bus. However two more dead clocks appear partially because the
memory controller must wait until the read data is removed from the XB1 to allow the write data to be latched
on the UPA side and partially because of the internal handshakes required by the coherency control, the port
interface and the memory controller. The dead clocks show up at the rst stretch point of the write cycle.
Also note that if a one timer nishes before the others in the DRAM cycle, the signal either stays in the nal
state or goes to the initial programed state. Overlapping signals is allowed if the overlapping signal timer is
nished however no practical application was found for this.
Note:
Factors for same group DRAM cycle concatenation:
DRAM control signal requirements (RAS and CAS precharge, address and data setup and hold time, signal
minimum width, minimum cycle time, and everything else in the DRAM specication).
UPA and XB1 timing for data transactions. (data oat time, correct data latch for writes and reads)
DSC control points (Setting Ping Pong points for address switching to the next cycle, setting stretch points
for holding cycles at the correct point for late data, starting and ending cycles at the right points).
Taking into account the special performance features of the SCMP (read cycles starting one clock early by
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