參數(shù)資料
型號(hào)： STP2202ABGA
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA320
封裝： BGA-320
文件頁(yè)數(shù)： 42/106頁(yè)
文件大?。?/td> 519K
代理商： STP2202ABGA
40
STP2202ABGA
Dual Processor System Controller
DSC
June 1998
Sun Microsystems, Inc
A non-optimized set of Memory CSR’s that work with the simulation environment is shown below. The clock
in this case is 50 MHz (20ns).
These CSR values were used when generating the following waveforms.
Writes to Different Groups
Figure 29 Illustrates two consecutive writes going to two different groups from different CPUs. The general
sequence is as follows:
1. The PM_ReqVal signal starts the MC FSM.
2. The mc_fsm sends out the start signal to Group 0 generators on the next clock.
3. The DPS tell the CPU to write to the XB1 write buffers on the next clock.
4. The Timers start counting.
5. The DPS tells the XB1 to accept the Write Data on the next clock.
6. WE_L is activated and remains so throughout the write cycle.
7. Another PM_ReqVal signal arrives, requesting group 1. Since SIMMBusyDiff is active, the next Write
cannot be started and the FSM goes into a Pending state.
8. SIMMBusyDiff is inactive on the next clock cycle and the start to group 1 is initiated.
9. And so on...
It may be possible to eliminate the “Pending” cycle by reducing the Diff_Busy_Wr_Wr count from a to 9 if the
memory address hold time does not get violated in the process. The memory address appears to be the limit-
ing factor in this case. Note that the DiffWr counter is held for one cycle in state 09. This is because the
DM_WBAck signal has not yet arrived and the state machines are held. See also Figure 35.
TABLE 1: CSR values for timing examples
Address
Value (Hex)
Function
80
a0c10f18
Mem_Control0
84
263725b3
RAS_Control
88
00004da3
CAS_RD_Control
8c
29362692
BankSel_Control
90
2c98249a
XB1_Buffer_Control
94
24cb24c7
CAS_WR_Control
98
14ac0279
Phase_Level_Control
9c
02952549
SIMM_Busy_Rd_Control
a0
06020543
Count_Control
a4
249324b7
Refresh_Control
a8
29b52493
Row_Control
b0
14952549
SIMM_Busy_Wr_Control
b4
12952549
SIMM_Busy_Refr_Control
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