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參數(shù)資料
| 型號： | STLC5411 |
| 廠商： | 意法半導體 |
| 英文描述： | 2B1Q U Interface Device(2BIQ U接口裝置) |
| 中文描述： | 2B1Q U接口設(shè)備（2BIQ ü接口裝置） |
| 文件頁數(shù)： | 26/72頁 |
| 文件大小： | 738K |
| 代理商： | STLC5411 |
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istersdescriptionfor details.
When NT1-AUTO or NT-RR-AUTO mode is se-
lected, bits ps1 and ps2 in M4 channel are con-
trolled directly by biasing input pins ES1 and ES2
respectively. e.g. ps1 is sent continuously to the
lineequal 0 when ES1 input is forced at 0 Volt.
Spare M5 and M6 bits
The spare bit positions in the M5 and M6 field
form a channel in which are transmitted data bits
loaded from the TXM56 transmit register. On the
receive side, the spare bits in the M5 and M6
field are first validated and then stored in the
RXM56 receive register. See OPR, TXM56 and
RXM56 registers description for details.
CRCcalculation/checking
In transmit direction, an on-chip CRC calculation
circuit automatically generatesa checksum of the
2B+D+M4 bits using the specified 12th order
polynomial. Once per superframe, the CRC is
transmitted in the M5 and M6 bit positions. In re-
ceive direction, a checksum is again calculated
on the same bits as they are received and, at the
end of the superframe compared with the re-
ceived CRC. The resultof this comparison gener-
ates a ”Far End Block Error” bit (febe) which is
transmitted back towards the other end of the
Line in the next but one superframe and an indi-
cation of Near End Block Error is sent to the sys-
tem by means of Register RXM56. If there is no
error in superframe, febe is set = 1, and if there is
one or more errors, febe is set = 0.
UID also includes two 8 bits Block Error Counters
associated with the febe bits transmitted and re-
ceived. It is then possible to select one Error
Counter per direction or to select only one counter
for both by meansof bitC2Ein OPR register. Block
error countingis alwaysenabledbutit is possibleto
disabled the threshold interrupt and/or to en-
able/disabletheinterrupt issuedat each received or
transmittedblock error detection.See OPR register
for details.
Loopbacks
Six transparent or non transparent channel loop-
backsare providedby UID. It is thereforepossibleto
operateanyloopbackonB1,B2 andD channelsline
to line or DSI/GCI to DSI/GCI. Command are
groupedinCR3 register.
In addition to the channel loopbacksin LTmodes,
a complete transparent loopback operated at the
transmission side of UID allows the device to acti-
vate through an appropriate sequence with the
complete data stream looped-back to the re-
ceiver. Therefore, most of analog/digitalclock and
data recovery circuits are tested. After activation
completed, an AI status indication is reported.
Completeloopbackis enabledwith ARL command
in TXACTregister.
STLC5411
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