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參數(shù)資料
| 型號： | STLC5411 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U Interface Device(2BIQ U接口裝置) |
| 中文描述： | 2B1Q U接口設(shè)備（2BIQ ü接口裝置） |
| 文件頁數(shù)： | 7/72頁 |
| 文件大?。?/td> | 738K |
| 代理商： | STLC5411 |
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PIN FUNCTIONS
(specific Micro Wire mode)
Pin
12
Name
BCLK
In/Out
In Out
Description
Bit clock input or output depending of the CMS bit in CMR register. When
BCLK is an input, its frequency may be any multiple of 8 KHz from 256 KHz
to 4096 KHz in formats 1, 2, 3; 512 KHz to 6176 KHz informat 4. When
BCLK is an output, its frequency is 256 KHz, 512 KHz, 1536 KHz, 2048
KHz or 2560 KHz depending of the selection in CR1 register. In this case,
BCLK is locked to the recovered clock received from the line. Input or
Output BCLK is synchronous with FSa/FSb. Datas are shifted in and out (on
Bx and Br) at the BCLK frequency in formats1, 2, 3. In format 4 datas are
shifted out at half the BCLK frequency.
2B+D input. Basic access data to transmit to the line is shiftedin on the
falling edges (at the BCLK frequency or the half BCLK frequency if format 4
is selected) during the assigned time-slots. When D channel port is
enabled, only B1 & B2 sampled on Bx.
D channel clock outputwhen the D channel port is enabled in continuous
mode. Datas are shifted in and out (on Dx and Dr) at 16 KHz on the falling
and rising edges of DCLK respectively. In master mode, DCLK is
synchronous with BCLK.
D channel data output when theD channel port is enabled. D channel data is
shiftedout from the UID on this pin in 2 selectable modes: in TDM mode data
is shifted out at the BCLKfrequency (or half BCLKfrequency informat 4) on
the ridsing edges when the assigned time slot is active. In continuous mode
dataisshifted out at the DCLK frequency on the rising edge continuously.
D channel data inputwhen the D channel port is enabled. D channel data is
shifted infrom the UID on this pin in 2 selectable modes: in TDM mode data
is shifted in at the BCLK frequency (or half BCLK frequency in format 4)on
the falling edges when the assigned time slot is active. In continuous mode
data is shiftedout at the DCLK frequency on the fallingedge continuously.
Clockinput for the MICROWIRE control channel: data is shifted in and out on
CI and CO pins with CCLK frequency following 2 modes. For each mode the
CCLKpolarity isindifferent. CCLK may be asynchronous with all the others
UID clocks.
MICROWIRE control channel serial input: Two bytes data is shifted out the
UID on this pin onthe rising or the falling edge of CCLK depending of the
working mode.
MICROWIRE control channel: serial output: two bytes data is shifted out the
UID on this pin onthe rising or the falling edge of CCLK depending of the
working mode. When not enabled by CS low, CO is high impedance.
Tx Super framesynchronization. The rising edge of SFSxindicates the
beginning of thetransmit superframe on theline. In NT mode SFSxis always
an output. In LT mode SFSxis an input or an output depending of the SFSbit
in CR2 register. When SFSx is input, it must besynchronous of FSa.
Rx Super frame synchronization. The rising edge of SFSr indicatesthe
begenning of the received superframe on the line. UID provides this output
only when ESFR bit in CR4 register is to 1.
Line Signal Detect output (default conf.): Thispin is an open drain output
which is normally in the high impedance state but pulls low when the device
previously in the power down state receives a wake-up by Tone from the
line. This signal is intended to be used to wake-up a micro-controller from a
low power idle mode. The LSD output goes back inthe high impedance
state when the device is powered up.
Interrupt output: Latched open-drain output signal which isnormally high
impedance and goes low to request a read cycle. Pending interrupt data is
shiftedout from CO at thefollowing read-write cycle. Several pending interrupts
may be queued internally and may provide several interrupt requests. INT is
freed upon receiving of CS low andcan goes lowagain when CS is freed.
Chip Select input: When this pin is pulled low, data can be shiftedin and out
from the UID through CI & CO pins. When high, this pin inhibits the
MICROWIRE interface. For normal read or write operation, CS has to be
pulled low for 16 CCLK periods of time.
13
Bx
In
14
DCLK
Out
15
Dr
Out
16
Dx
In
17
CCLK
In
18
CI
In
19
CO
Out
22
SFSx
In Out
25
SFSr
Out
LSDb
Out
26
INTb
Out
27
CS
In
STLC5411
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| STLC5411CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface |
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