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參數(shù)資料
| 型號(hào)： | STLC5411 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U Interface Device(2BIQ U接口裝置) |
| 中文描述： | 2B1Q U接口設(shè)備（2BIQ ü接口裝置） |
| 文件頁(yè)數(shù)： | 21/72頁(yè) |
| 文件大小： | 738K |
| 代理商： | STLC5411 |
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Data is transmitted in both directions at half the
data clock rate. The information is clocked by the
transmitteron the front edge of the data clock and
can be accepted by the receiver after 1 to 1.5 pe-
riod of the data clock.
The data clock (BCLK) is a square wave signal at
twice the data transmission frequency on Bx and
Br with a 1 to 1 duty cycle. The frequencycan be
choosen from 512
to 6176 kHz with 16 kHz
modularity. Data transmission rate depends only
on the data clock rate.
The Frame Clock FSa is a 8 kHz signal for syn-
chronization of data transmission. The front edge
of this signal gives the time reference of the first
bit in the first GCI input and output channel, and
reset the slot counterat thestart of eachframe
When some GCI channels are not selected on
devices connected to the same GCI link, these
time slots are free for alternativeuses.
GCI configuration selection is done by biasing of
input pins MW, M0, CONF1, CONF2 according to
TABLE1.
Table 1:
GCIConfigurationselection.
Pin Number
Pin name
Configuration
LT/NT12*
NT/TE
NT1-AUTO
LT-RR-AUTO
NT-RR-AUTO
28
MW
0
0
0
0
0
27
M0
0
1
1
1
1
19
S1/CONF1
S1
0
1
1
0
17
S2/CONF2
S2
1
1
0
0
7
S0/FSb/TEST2
S0
FSb
TEST2
TEST2
TEST2
18
IO1/ES1
IO1
IO1
ES1
PLDD
ES1
16
IO2/ES2
IO2
IO2
ES2
EC
ES2
15
IO3/EC
IO3
IO3
EC
LFS
LFS
14
IO4/TEST1
IO4
IO4
TEST1
TEST1
TEST1
22
SFSx/RFS
SFSx
SFSx
SFSx
RFS
RFS
* Differentationbetween LT and NTconfigurationdone by bit NTS in CR2 register;GCI in slavemode.
When NT1-AUTO or NT-RR-AUTO configuration is selected, BCLK bit clock frequency of 512 kHz is
automaticallyselected
When NT configurationis selected,BCLK bit clock frequencyof 1536 kHz is automaticallyselected.
* *Connected to V
CC
throughinternal pull-up resistors.
STLC5411
21/72
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