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參數(shù)資料
| 型號： | STLC5411 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U Interface Device(2BIQ U接口裝置) |
| 中文描述： | 2B1Q U接口設(shè)備（2BIQ ü接口裝置） |
| 文件頁數(shù)： | 42/72頁 |
| 文件大?。?/td> | 738K |
| 代理商： | STLC5411 |
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and M56, both registers RXM4 and RXM56 are
queuedin the interrupt register stack.
Bits act, dea, uoa, sai arededicated to the activa-
tion procedure. Validation is always done in ac-
cordance with the ANSI rule: validation at each
new activation bit received and confirmed twice
independently from the above rules. These bits
are taken into account directly by the activation
decoder. An interrupt is not generated for the
RXM4 Register when one of these bits changes,
but they are provided for test to the RXM4 Regis-
ter.
OC1, OC0
eoc channelprocessing:
select how a received eoc message is validated
and transmitted to the system.
OC1
0
OC0
0
every half a super frame, an
interrupt is generated for the
RXEOC register. eoc channel
is transparently transmitted to
the system.
an interrupt is set at each new
eoc message received.
an interrupt is set at each new
eoc message received and
confirmed once. (two times
identical)
an interrupt is set at each new
eoc message received and
confirmed twice. (three times
identical).
0
1
1
0
1
1
C2E
Counter2 enable:
C2E = 0: Only counter BEC1 is used for both febe
and nebe counting.
C2E = 1: Counter BEC1 is used for nebe.
Counter BEC2is used forfebe.
Configuration register 1 (CR1)
After reset:
μ
W mode 00H
GCI: MO = 0 (LT/NT12) = C0H
GCI: MO = 1 (NT/TE) = D2H
FF1
FF1, FF0
Frame Format Selection:(
μ
W/DSIonly)
Refer to fig. 2and 3.
FF0
CK2
CK1
CK0
DDM
CMS
BEX
FF1
0
0
1
1
FF2
0
1
0
1
Format 1
Format 2
Format 3
Format 4
CK0-CK2
Digital Interface Clock select: (mW/DSI
only)
CK0-CK2 bits select the BCLK output frequency
when DSI clocks are outputs.
CK2
0
0
0
0
1
CK1
0
0
1
1
0
CK0
0
1
0
1
0
BCLK frequency:
256KHz
512KHz
1536KHz
2048KHz
2560KHz
DDM
DelayedData Mode select:(
μ
W/DSI only)
Two different phase-relations may be established
between the Frame Sync signals and the first bit
of the frame on theDigital Interface:
DDM = 0: Non delayed data mode The first bit
of
the
frame
coincident with the rising edge of
FSA/B.
DDM = 1: delayed data mode: FSA/B input must
be set high at least a half cycle of
BCLK earlier the frame beginning.
CMS
Clocks Master Select:(
μ
W/DSI only)
begins
nominally
CMS = 0: BCLK, FSA and FSB are inputs;
BCLK can have in Format 1, 2 and 3
value between 256KHz to 4096KHz,
value
in
Format
6176KHz.
CMS = 1: BCLK, FSA andFSB are outputs; FSA
is a 8 kHz clock pulse indicating the
frame beginning, FSB is a 8 kHz clock
pulse is indicating the second 8 bits
wide time-slot. BCLK is a bit clock
signal whose frequencybits CK2-CK0.
BEX
B channelsExchange:
4:
512KHz
to
BEX = 0: B1
and
B2
Tx/Rx
with
channels are
TXB1/RXB1
associated
TXB2/RXB2 registersrespectively.
BEX = 1: B1 andB2 channelsare exchanged.
Configuration register 2 (CR2)
After reset:
μ
W mode 00H
GCI: MO = 0 (LT/NT12)= 00H
GCI: MO = 1 (NT/TE) = 80H
μ
W (LT,NT):
and
SFS NTS DMO DEN ETC
BP1
EIF
BP2
BFH9D
RR
GCI (LT,NT):
SFS NTS T24D CID
ETC
BP1
EIF
BP2
BFH9D
RR
SFS
Super Frame SynchronizationSelect:
Significant inLT mode only.
STLC5411
42/72
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