參數(shù)資料
型號(hào)： STLC5411
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U Interface Device(2BIQ U接口裝置)
中文描述： 2B1Q U接口設(shè)備（2BIQ ü接口裝置）
文件頁數(shù)： 40/72頁
文件大小： 738K
代理商： STLC5411
0101 (PDN):
PowerDown
PDN command forces UID to power down state. It
should normally be used after UID has been set
in a known deactivatedstate, e.g. in an LT aftera
DI statusindication has been reported. In GCI, C/I
indicationDI is sent twice on Br outputbefore UID
powersdown.
0110 (UAR):
U-interface-only Activation Request
Being Power Up and deactivated , UAR com-
mand forces UID through the appropriate se-
quence to activate the loop without activating the
S/T interface. SL2/SL3 signal is sent with uoa bit
set to zero. With the line already active, UAR
command forces bit uoa equal zero: this is in-
tended to deactivatethe S/Tinterface.
0111 (QM):
QuietMode
This command has the same effect as in NT
mode.
1000 (AR):
ActivationRequest
Being Power Up and deactivated, AR instruction
forces UID through the appropriate sequence to
activate the line by sending TL followed by SL1.
SL2/SL3signal is sent with uoa bitequal one.
Beeing in the U-only-active states, AR command
forces the uoa bit equal 1 to the line. Is intended
to activate the S/T interface.
1010 (ARL):
Activation Request with Loopback
ARL test command forces UID through the appro-
priate sequence to activate with the complete
transmit data stream looped-back to the receiver.
When this loop-back is disabledby DR command,
UID is ready to operate a warm startif a new ARL
command is issued.
1011 (SP3):
Send SinglePulse +3, -3
SP3 test command forces UID to
pulses to the line, one pulse per frame.
1100 (AI):
ActivationIndicate
AI is an optional command recognized only when
BP2 bit in CR2 register is set equal one or LT-
RR-AUTO mode is selected. Beeing in the super-
frame-synchronized state with act bit received
from the line equal one, AI command allows UID
to send actbit equal one to the line.
1111 (DI):
DeactivationIndicate
The DI command allows the UID to automatically
enter the power down state if the line is deacti-
vated. DI command has no effect as long as the
line is not deactivated (DI status indication re-
ported).
send +3, -3
LT mode: Status indication
0001 (EIU):
Error IndicationInterfaceU
EIU status indication reports an error at U inter-
face. It can be a ‘loss at signal‘ a ‘loss of
sync‘,‘expiry of Timer 4 lias reset UID for cold-
start‘ and ‘UID put in receive reset state by RES
command‘.
0100 (EI):
ErrorIndication
EI status indication reports that act bit has been
detected equal zero.
0110 (UAI):
U interfaceActivation Indication
UAI reports that the line is superframe synchro-
nized.
1000 (AP):
Activation Pending
Being in one of the deactivatedstates, AP reports
that a wake up tone has been detected from the
line. Beeing in the U-only-activated state, AP re-
ports that sai bit has been detected equal one
from the line. Is intended to reflect an activation
attempt at the S/T interface.
1100 (AI):
ActivationIndication
AI reports that UID is superframe synchronized
with act bit received equal one. TE side of the
loop relative to the UID is active
1111 (DI):
Deactivation Indication DI reports that
UID has entered the deactivatedstate (J1).
B1, B2 and D channelstransparency
UID is able to control automatically transparency of
B1, B2 and D channels. Nevertheless, when ETC
bit in CR2 register is set equal 1, transparency is
forced assoon as the line is synchronized.
It is also possible to control each data channel B1,
B2, D enabling at the DSI/GCI interface inde-
pendently by means of bits EB1, EB2 and ED in
CR4 register; Set equal 1, B1, B2 or D channelon
the DSI/GCI interface is enabled; In this case, out
of the transparency state (s), ones are forced on
thee relevant time slot of the DSI/GCI, and ones or
zeros are transmittedon the line conforming T1E1
recommendations. Set equal 0, relevant time slot
on DSI/GCI is always in high impedancestate and
ones or zerosare transmittedon theline. In thislast
case,as soonas transparencyis enabled,onesare
transmittedto the line.
When RDT test command is applied, transpar-
ency on 2B+D is forced. This intend to permit the
user, if required, to send a random sequence of
bits to the line. Please note that the on-chip
scrambler
normally
ensures transmission
equiprobable levels to the line, even if logical one
only is provided to theDSI/GCI system interface.
of
INTERNAL REGISTERSDESCRIPTION.
Here
following
a
STLC5411internal registers.
Internal registers can be accessed:
a) In GCI mode, according to the monitor channel
exchange rules. For RXACT and TXACT also
through C/I channel.
b) in
μ
W/DSI mode, using the MICROWIRE inter-
face according to the rules described in section
”
μ
W controlinterface”.
Table 8 givesthe list of all the STLC5411internal
registers can be used in MICROWIRE mode.
Table 9 givesthe list of all the STLC5411internal
registers can be used in GCI mode.
Registers are grouped by types and address ar-
detailed
description
of
STLC5411
40/72
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