參數(shù)資料
型號(hào)： STLC5411
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U Interface Device(2BIQ U接口裝置)
中文描述： 2B1Q U接口設(shè)備（2BIQ ü接口裝置）
文件頁(yè)數(shù)： 61/72頁(yè)
文件大?。?/td> 738K
代理商： STLC5411
TIMING CHARACTERISTICS
Symbol
MASTERCLOCK
FMCLK
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Frequency of MCLK
Tolerance
MCLK/XTAL Input Clock Jitter
Clock Pulse Width, MCLK High Level
Clock Pulse Width, MCLK Low Level
Rise Time of MCLK
Fall Time of MCLK
DIGITALINTERFACE
FBCLK
Frequency of BCLK
Including Temperature,
Aging, Etc...
External Clock Source
V
IH
= V
CC
– 0.5V
V
IL
= 0.5V
–100
15.36
+100
50
MHz
ppm
nspk-pk
ns
ns
ns
ns
tWMH
tWML
tRM
tFM
20
20
Used as a Logic Input
10
10
Formats 1, 2 and 3
Format 4 and GCI Mode
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
DSI or GCI Slave Mode only
DSI or GCI Slave Mode only
DSI orGCI Master Modeonly
Load=150pF+2LSTTLLoads(*
256
512
30
30
4095
6144
KHz
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWBH
tWBL
tRB
tFB
tSFB
tHBF
tDBF
tDBD
tDBDZ
tDFD
tSDB
tHBD
tDBT
tDBTZ
tDFT
D PORT IN CONTINUOUS MODE: 16KBITS/SEC
tSDD
SetupTime, DCLK Low toDX High orLow
tHDD
HoldTime, DCLK Low to DX High orLow
tDDD
Delay Time,DCLK High toDRHighorLow
MICROWIRE CONTROL INTERFACE
FCCLK
Frequency of CCLK
tWCH
Clock Pulse Width, CCLK High Level
tWCL
Clock Pulse Width, CCLK Low Level
tRC
Rise Time of CCLK
tFC
Fall Time of CCLK
tSSC
Setup Time, CSB Low to CCLK High
tHCS
Hold Time, CCLK Low to CSB High
tWSH
Duration of CSB High
tSIC
Setup Time, CI Valid to CCLK High
tHCI
Hold Time, CCLK High to CI Invalid
tDSO
Delay Time, CSB Low to CO Valid
tDCO
Delay Time CCLK Low to CO Valid
tDCOZ
Delay Time, CCLK Low to CO HZ
tDCI
Delay Time,CCLK Low toINTBLowor HZ
(* In GCImode: Load Res.
Clock Pulse Width, BCLK High Level
Clock Pulse Width, BCLK Low Level
Risae Time of BCLK
Fall Time of BCLK
SetupTime, FSHigh or Low toBCLK Low
Hold Time, BCLK Lowto FS High or Low
Delay Time,BCLK High toFS High or Low
Delay Time, BCLK High to Data Valid
Delay Time, BCLK High to Data HZ
Delay Time, FS High to Data Valid
Setup Time, Data Valid to BCLK Low
Hold time, BCLK to Data Invalid
Delay Time, BCLK High to TSR Low
Delay Time, BCLK Low to TSR HZ
Delay Tie, FS High to TSR Low
15
15
30
20
–20
20
80
50
80
Load=150pF +2LSTTLLoads
0
20
Load=100pF +2LSTTLLoads
80
50
80
Load=100pF +2LSTTLLoads
50
50
ns
ns
ns
Load = 50pF +2 LSTTLLoads
80
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
85
85
15
15
60
10
200
25
25
Out First Bit on CO
Load = 50pF + 2LSTTL Loads
50
50
50
50
Load = 80pF + 2LSTTL Loads
STLC5411
61/72
相關(guān)PDF資料
PDF描述
STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412FN 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412P 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5444 Quad Feed Power Supply(ISDN四饋電電源)
STLC5460 Line Card Interface Controller(線路卡片接口控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
STLC5411CJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface
STLC5411FN 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE
STLC5411P 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE
STLC5412 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412FN 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*