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參數(shù)資料
| 型號： | STLC5411 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2B1Q U Interface Device(2BIQ U接口裝置) |
| 中文描述： | 2B1Q U接口設(shè)備（2BIQ ü接口裝置） |
| 文件頁數(shù)： | 23/72頁 |
| 文件大?。?/td> | 738K |
| 代理商： | STLC5411 |
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on Br is in the high impedancestate.
A 24 ms timer is implemented in the UID. This
timer (when enabled) starts each time the sender
starts a byte sending and waits for a pre acknow-
ledgement.
C/I channel
The C/I channel is used for TXACT and RXACT
registers write and read operation. However, it is
possible to access to ACT registers by monitor
channel: this access is controled by the CID bit in
CR2 register.
The four bits code (C1,C2,C3,C4) of TXACT reg-
ister can be loaded in the UID by writing perma-
nently this code in the C/I channel time-slot on Bx
input every GCI frames. The UID takes into ac-
count the received code when it has been re-
ceived two consecutive times identical. When a
status change occurs in the RXACT register, the
new (C1,C2,C3,C4) code is sent in the C/I chan-
nel time-slot on Br output every GCI frames. This
E & A BITS TIMING
TWO BYTES MESSAGE ABORTED ON THE SECOND AND RETRANSMITTED
TWO BYTES MESSAGE - NORMAL TRANSMISSION
(M1)
X
M1
M
E
A
M1
M2
M2
X
X
X
1st byte
(M1)
pre-ack
ack
(M1)
2nd byte
(M2)
pre-ack
(M2)
ack
(M2)
3rd byte
(X)
pre-ack
(X)
EOM
Ready for
a new message
Ready
for a message
M
E
A
1st byte
(M1)
pre-ack
(M1)
ack
(M1)
2nd byte
(M2)
pre-ack
(M2)
abort
(M2)
EOM
(or abort ack)
1st byte
(M1)
pre-ack
(M1)
3rd byte
(X)
Ready for
retransmission
Ready for
a message
X
M1
M1
M2
M2
X
X
X
X
M1
M1
M2
Figure 5:
GCIMonitor channelmessaging examples.
STLC5411
23/72
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