參數(shù)資料
型號(hào)： STLC5411
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U Interface Device(2BIQ U接口裝置)
中文描述： 2B1Q U接口設(shè)備（2BIQ ü接口裝置）
文件頁數(shù)： 15/72頁
文件大?。?/td> 738K
代理商： STLC5411
To read a 12 bitsmessage,the differenceis:
limited address field:
extendeddata field (D11- D8):A3 - A0.
The Write/Read back indicator doesn‘texit.
A7 - A4
DIGITAL SYSTEM INTERFACE
Two B channels,eachat 64 kbit/sand one D chan-
nel at 16 kbit/s form the Basic access data. Basic
accessdatais transferredon the Digital System In-
terface with several different formats selectable by
meansof the configurationregister CR1.
The DSI is basically constituted of 5 wires (see
fig.2 and 3):
BCLK
Bx
Br
FSa
FSb
bit clock
data input to transmit to the line
data output received from the line
Transmit Frame sync
Receive Frame sync
It is possible to separate the D channelfrom the B
channels and to transfer it on a separate Digital
Interfaceconstitutedof 2 pins:
Dx
Dr
D channel datainput
D channel dataouput
The TDM (Time Division Multiplex) mode uses
the same bit and frame clocks as for the B chan-
nels. The continuous mode uses an internally
generated16 kHz bit clock output:
DCLK
D channel clock output
For all formats when D channel port is enabled
”continuous mode” is possible.When the D chan-
nel port is enabled in TDM mode, D bits are as-
signed according to the related format on Dx and
Dr .
STLC5411 provides a choice of four multiplexed
formats for the B and D channels data as shown
in fig.2 and3.
Format 1:
the 2B+D data transfer is assigned to
the first 18 bits of the frame on Br and Bx I/0 pins.
Channels are assigned as follows: B1(8 bits),
B2(8 bits), D(2 bits), with the remaining bits ig-
noreduntil the next Frame sync pulse.
Format 2:
the 2B+D data transfer is assigned to
the first 19 bits of the frame on Br and Bx I/O
pins. Channels are assigned as follows: B1(8
bits), D(1 bit), 1 bit ignored, B2(8 bits), D(1 bit),
with the remaining bits ignored until the next
frame sync pulse.
Format 3:
B1 and B2 Channels can be inde-
pendently assigned to any 8 bits wide time slot
among 64 (or less) on the Bx and Br pins. The
transmit and receive directions are also inde-
pendent. When TDM mode is selected, the D
channel can be assigned to any 2 bits wide time
slot among 256 on the Bx and Br pins or on the
Dx and Dr pins (D port disabled or enabled in
TDM mode respectively).
Format 4:
is a GCI like format excluding Monitor
channel and C/I channel. The 2B+D data transfer
is assigned to the first 26 bits of the frame on Br
and Bx I/O pins. Channels are assigned as fol-
lows. B1(8 bits) B2(8 bits), 8 bits ignored, D(2
bits), with remaining bits ignored up to the next
frame sync pulse.
When the Digital Interface clocks are selected as
inputs, FSa must be a 8 kHz clock input which in-
dicates the startof the frameon the data input pin
Bx. When the Digital Interfaceclocks are selected
as outputs, FSa is an 8 kHz output pulse con-
forming to
the selected format which indicates
the frame beginning for both Tx and Rx direc-
tions.
When the Digital Interface clocks are selected as
inputs, FSb is a 8 kHz clock input which defines
the start of the frame on the data ouput pin Br.
When the Digital Interface clocks are selected as
outputs, FSb is a 8 kHz output pulse indicating
the second64kbit/s slot.
Two phase-relations between the rising edge of
FSa/FSb and the first (or second for FSb as out-
put) slot of the frame can be selected depending
on format selected: Delayed timing mode or non
Delayed timing mode.
Non delayed data mode is similar to long frame
timing on the COMBOI/II series of devices: The
first bit of the frame begins nominally coincident
with the rising edge of FSa/b. When output, FSa
is coincident with the first 8 bits wide time-slot
while FSb is coincident with the second 8 bits
wide time-slot. Non delayed mode is not available
in format2.
Delayed timing mode, which is similar to short
frame sync timing on COMBO I/II, in which the
FSa/b input must be set high at least a half cycle
of BCLK earlier the frame beginning. When out-
put, FSa 1bit wide pulse indicates the first 8 bits
wide time-slot while FSb indicates the second.
Delayed mode is not availablein format 4.
2B+D basic access data to transmit to the line
can be shifted in at the BCLK frequency on the
falling edges during the assigned time-slots.
When D channel port is enabled, only B1 & B2
data is shiftedin during the assigned time slots. In
format 4, data is shifted in at half the BCLK fre-
quency on the receive falling edges.
2B+ D basic access data received from the line
can be shiftedout from the Broutput at the BCLK
frequency on the rising edges during the assigned
time-slots. Elsewhere, Br is in the high impedance
state. When the D channel port is enabled, only
B1 & B2 data is shifted out from Br. In Format 4,
data is shifted out at half the BCLK frequency on
the transmit risingedges; thereis 1.5 period delay
between the rising transmit edge and the receive
falling edge of BCLK.
STLC5411
15/72
相關(guān)PDF資料
PDF描述
STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412FN 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412P 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5444 Quad Feed Power Supply(ISDN四饋電電源)
STLC5460 Line Card Interface Controller(線路卡片接口控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
STLC5411CJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface
STLC5411FN 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE
STLC5411P 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE
STLC5412 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412FN 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*