參數(shù)資料
型號: STLC5411
廠商: 意法半導體
英文描述: 2B1Q U Interface Device(2BIQ U接口裝置)
中文描述: 2B1Q U接口設(shè)備(2BIQ ü接口裝置)
文件頁數(shù): 49/72頁
文件大?。?/td> 738K
代理商: STLC5411
EOC
ReceiveEOC status register read.
When EOC bit is setequal one, UID automatically
loads the current value of RXEOC register in the
interrupt stack
independently of
change.
any status
M4
Receive M4 overhead bits status register
read.
When M4 bit is set equal one, UID automatically
loads the current value of RXM4 register in the in-
terrupt stackindependentlyof any statuschange.
M56
Receive M5 and M6 overhead bits status
registerread.
When M56 bitis set equal one, UID automatically
loads the current value of RXM56 register in the
interrupt stack
independently of
change.
any status
ACT
Activationindication status.
When ACT bit is set equal one, UID automatically
loads the current value of RXACT register in the
interrupt stack
independently of
change.
In GCI mode, the RXACT read back always uses
the monitor channel.
any status
STATUS
When STATUS bit is set egal one, UID automat-
ically loads the current value of STATUS register
in the interrupt stack independentlyof any status
change.
RST
only).
When RST bit is set equal one, UID is fully reset
including configuration registers, state machine
and all coefficients and reset to their default
value. UID entersin the power-downstate.
RESET
(MICROWIRE/DSI
configuration
Transmit EOC register (TXEOC)
After reset: FFFH
XEOC1
XEOC2
XEOC3
XEOC4
XEOC5
XEOC6
XEOC7
XEOC8
TXEOC Register is constituted of 12 bits, 3 bits
address (EFG), 1 bit data/message Flag (H), 8
bits information (XEOC1 - XEOC8). When trans-
mitting SL2/SL3 or SN3 signal. STLC5411 shall
continuously send into the EOC channel field the
eoc bits twice per superframe. TXEOC register is
loaded in the transmit register at each half a su-
perframe.
The address of this register is composed only of 4
bits. Read-back can be performed by means of a
read-back command 6100H.
Receive EOCregister (RXEOC)
(read only)
After reset: FFFH
REOC1
REOC2
REOC3
REOC4
REOC5
REOC6
REOC7
REOC8
The RX EOC Register is constituted of 12 bits.
When the line is fully activated (super frame syn-
chronized) and when a new eoc message is re-
ceived and validated in accordancewith the crite-
ria selected in the Configuration Register OPR,
the RX EOC Register is queued in the interrupt
register stack. The address of this registeris com-
posed only of 4 bits.
It is always possible to read this register by writ-
ing RXEOC = 1 inRXOH register
Identification Register (IDR)
Fixed value: 08H
(read only)
When a read-backoperation of IDR register is en-
tered, UID loads the IdentificationRegister in the
interrupt stack. This register provides a reserved
identificationcode agreed by GCI standard:08H.
IDR registeris accessible via two addresses.
MWPS Micro Wire Port Select register (Signifi-
cant in microwiremode only).
(write only)
Default value: Mode A(5410 compatible)
– Writting FFH value select the mode B to ex-
changedata onto CI & CO
– Writing00H value select the mode A (See Mi-
crowire control interface paragraph for more
detailsMode A, Mode B).
Note: Soft Reset has no effect on the select
mode.
STLC5411
49/72
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