參數(shù)資料
型號: ST72T631K2M0
廠商: 意法半導(dǎo)體
英文描述: LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
中文描述: 低速USB 8高達(dá)16K的內(nèi)存位微控制器系列,高達(dá)512字節(jié)RAM,8位ADC,水分散粒劑,定時器,SCI
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文件大?。?/td> 857K
代理商: ST72T631K2M0
ST7263
85/109
8-BIT A/D CONVERTER (ADC)
(Cont’d)
5.8.3 Functional Description
The high level reference voltage V
DDA
must be
connected externally to the V
DD
pin. The low level
reference voltage V
SSA
must be connected exter-
nally to the V
SS
pin. In some devices (refer to de-
vice pin out description) high and low level refer-
ence voltages are internally connected to the V
DD
and V
SS
pins.
Conversion accuracy may therefore be degraded
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
Figure 43. Recommended Ext. Connections
Characteristics:
The conversion is monotonic, meaning the result
never decreases if the analog input does not and
never increases if the analog input does not.
If input voltage is greater than or equal to V
DD
(voltage reference high) then results = FFh (full
scale) without overflow indication.
If input voltage
V
SS
(voltage reference low) then
the results = 00h.
The conversion time is 64 CPU clock cycles in-
cluding a sampling time of 31.5 CPU clock cycles.
R
AIN
is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
The A/D converter is linear and the digital result of
the conversion is given by the formula:
Where Reference Voltage is V
DD
- V
SS
.
The accuracy of the conversion is described in the
Electrical Characteristics Section.
Procedure:
Refer to the CSR and DR register description sec-
tion for the bit definitions.
Each analog input pin must be configured as input,
no pull-up, no interrupt. Refer to the “I/O Ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
In the CSR register:
– Select the CH2 to CH0 bits to assign the ana-
log channel to convert. Refer to
Table 21
Channel Selection
.
– Set the ADON bit. Then the A/D converter is
enabled after a stabilization time (typically 30
μs). It then performs a continuous conversion
of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register.
A write to the CSR register aborts the current con-
version, resets the COCO bit and starts a new
conversion.
5.8.4 Low Power Modes
Note:
The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
5.8.5 Interrupts
None.
ST7
Px.x/AINx
V
DDA
V
SSA
V
DD
0.1μF
R
AIN
V
AIN
Digital result = 255 x Input Voltage
Reference Voltage
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
before accurate conversions can be
performed.
HALT
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