參數(shù)資料
型號: ST72T631K2M0
廠商: 意法半導體
英文描述: LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
中文描述: 低速USB 8高達16K的內(nèi)存位微控制器系列,高達512字節(jié)RAM,8位ADC,水分散粒劑,定時器,SCI
文件頁數(shù): 18/109頁
文件大小: 857K
代理商: ST72T631K2M0
ST7263
18/109
3.2 RESET
The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.
Three reset modes are provided: a low voltage
(LVD) reset, a watchdog reset and an external re-
set at the RESET pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 4096 CPU clock cy-
cle delay from the time that the oscillator becomes
active.
3.2.1 Low Voltage Detector (LVD)
Low voltage reset circuitry generates a reset when
V
DD
is:
I
below V
IT+
when V
DD
is rising,
I
below V
IT-
when V
DD
is falling.
During low voltage reset, the RESET pin is held low,
thus permitting the MCU to reset other devices.
The Low Voltage Detector can be disabled by set-
ting the LVD bit of the Miscellaneous Register.
3.2.2 Watchdog Reset
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devic-
es in the same way as the low voltage reset (
Fig-
ure 11
).
3.2.3 External Reset
The external reset is an active low input signal ap-
plied to the RESET pin of the MCU.
As shown in
Figure 14
, the RESET signal must
stay low for a minimum of one and a half CPU
clock cycles.
An internal Schmitt trigger at the RESET pin is pro-
vided to improve noise immunity.
Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.5 for Wait and Halt Modes)
Section
RESET
WAIT
HALT
CPU clock running at 8 MHz
X
Timer Prescaler reset to zero
X
Timer Counter set to FFFCh
X
All Timer enable bit set to 0 (disable)
X
Data Direction Registers set to 0 (as Inputs)
X
Set Stack Pointer to 013Fh
X
Force Internal Address Bus to restart vector FFFEh,FFFFh
X
Set Interrupt Mask Bit (I-Bit, CCR) to 1 (Interrupt Disable)
X
Set Interrupt Mask Bit (I-Bit, CCR) to 0 (Interrupt Enable)
X
X
Reset HALT latch
X
Reset WAIT latch
X
Disable Oscillator (for 4096 cycles)
X
X
Set Timer Clock to 0
X
X
Watchdog counter reset
X
Watchdog register reset
X
Port data registers reset
X
Other on-chip peripherals: registers reset
X
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