參數(shù)資料
型號(hào): ST72T631K2M0
廠商: 意法半導(dǎo)體
英文描述: LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
中文描述: 低速USB 8高達(dá)16K的內(nèi)存位微控制器系列,高達(dá)512字節(jié)RAM,8位ADC,水分散粒劑,定時(shí)器,SCI
文件頁數(shù): 79/109頁
文件大?。?/td> 857K
代理商: ST72T631K2M0
ST7263
79/109
I2C BUS INTERFACE
(Cont’d)
5.7.7 Register Description
I2C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 =
PE
Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes
:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– To enable the I2C interface, write the CR register
TWICE
with PE=1 as the first write only activates
the interface (only PE is set).
Bit 4 =
ENGC
Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Bit 3 =
START
Generation of a Start condition
.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation
1: Start generation when the bus is free
Bit 2 =
ACK
Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 1 =
STOP
Generation of a Stop condition
.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
– In Master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– In Slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
Bit 0 =
ITE
Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to
Figure 4
for the relationship between the
events and the interrupt.
SCL is held low when the SB, BTF or ADSL flags
or an EV6 event (See
Figure 3
) is detected.
7
0
0
0
PE
ENGC START
ACK
STOP
ITE
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