參數(shù)資料
型號(hào): ST72T631K2M0
廠商: 意法半導(dǎo)體
英文描述: LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
中文描述: 低速USB 8高達(dá)16K的內(nèi)存位微控制器系列,高達(dá)512字節(jié)RAM,8位ADC,水分散粒劑,定時(shí)器,SCI
文件頁(yè)數(shù): 63/109頁(yè)
文件大小: 857K
代理商: ST72T631K2M0
ST7263
63/109
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
DATA REGISTER (DR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 1).
BAUD RATE REGISTER (BRR)
Read/Write
Reset Value: 00xx xxxx (XXh)
Bits 7:6=
SCP[1:0]
First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bits 5:3 =
SCT[2:0]
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits, define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Bits 2:0 =
SCR[2:0]
SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits, define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
7
0
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
PR Prescaling Factor
1
3
4
13
SCP1
0
0
1
1
SCP0
0
1
0
1
TR Dividing Factor
1
2
4
8
16
32
64
128
SCT2
0
0
0
0
1
1
1
1
SCT1
0
0
1
1
0
0
1
1
SCT0
0
1
0
1
0
1
0
1
RR Dividing Factor
1
2
4
8
16
32
64
128
SCR2
0
0
0
0
1
1
1
1
SCR1
0
0
1
1
0
0
1
1
SCR0
0
1
0
1
0
1
0
1
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