參數(shù)資料
型號(hào): ST72T631K2M0
廠商: 意法半導(dǎo)體
英文描述: LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
中文描述: 低速USB 8高達(dá)16K的內(nèi)存位微控制器系列,高達(dá)512字節(jié)RAM,8位ADC,水分散粒劑,定時(shí)器,SCI
文件頁(yè)數(shù): 62/109頁(yè)
文件大?。?/td> 857K
代理商: ST72T631K2M0
ST7263
62/109
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: Undefined
Bit 7 =
R8
Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 =
T8
Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
Bit 5 = Reserved, forced by hardware to 0.
Bit 4 =
M
Word length.
This bit determines the data length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 3 =
WAKE
Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
1: Address Mark
Bits 2:0 = Reserved, forced by hardware to 0.
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 =
TIE
Transmitter interrupt enable
.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register.
Bit 6 =
TCIE
Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SR register
Bit 5 =
RIE
Receiver interrupt enable
.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SR register
Bit 4 =
ILIE
Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SR register.
Bit 3 =
TE
Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to
the I/O port configuration.
1: Transmitter is enabled
Note:
During transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 2 =
RE
Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,
OR, NF and FE bits of the SR register.
1: Receiver is enabled and begins searching for a
start bit.
Bit 1 =
RWU
Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 0 =
SBK
Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note:
If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
7
0
R8
T8
0
M
WAKE
0
0
0
7
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
相關(guān)PDF資料
PDF描述
ST72T631K2M1 LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
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