參數(shù)資料
型號(hào): ST72T631K2M0
廠商: 意法半導(dǎo)體
英文描述: LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
中文描述: 低速USB 8高達(dá)16K的內(nèi)存位微控制器系列,高達(dá)512字節(jié)RAM,8位ADC,水分散粒劑,定時(shí)器,SCI
文件頁(yè)數(shù): 70/109頁(yè)
文件大?。?/td> 857K
代理商: ST72T631K2M0
ST7263
70/109
USB INTERFACE
(Cont’d)
ENDPOINT n REGISTER B (EPnRB)
Read / Write
Reset Value: 0000 xxxx (0xh)
These registers (
EP1RB
and
EP2RB
) are used for
controlling data reception on Endpoints 1 and 2.
They are also reset by the USB bus reset.
Note
: Endpoint 2 and the EP2RB register are not
available on some devices (see device feature list
and register map).
Bit 7 =
CTRL
Control.
This bit should be 0.
Note:
If this bit is 1, the Endpoint is a control end-
point. (Endpoint 0 is always a control Endpoint, but
it is possible to have more than one control End-
point).
Bit 6 =
DTOG_RX
Data toggle, for reception trans-
fers
.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP trans-
actions start always with DATA0 PID). The receiv-
er toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
Bits 5:4 =
STAT_RX [1:0]
Status bits, for reception
transfers.
These bits contain the information about the end-
point status, which are listed below:
These bits are written by software. Hardware sets
the STAT_RX bits to NAK when a correct transfer
has occurred (CTR=1) related to an OUT or SET-
UP transaction addressed to this endpoint, so the
software has the time to elaborate the received
data before acknowledging a new transaction.
Bits 3:0 =
EA[3:0]
Endpoint address
.
Software must write in this field the 4-bit address
used to identify the transactions directed to this
endpoint. Usually EP1RB contains “0001” and
EP2RB contains “0010”.
ENDPOINT 0 REGISTER B (EP0RB)
Read / Write
Reset Value: 1000 0000 (80h)
This register is used for controlling data reception
on Endpoint 0. It is also reset by the USB bus re-
set.
Bit 7 = Forced by hardware to 1.
Bits 6:4 = Refer to the EPnRB register for a de-
scription of these bits.
Bits 3:0 = Forced by hardware to 0.
7
0
CTRL
DTOG
_RX
STAT
_RX1
STAT
_RX0
EA3
EA2
EA1
EA0
STAT_RX1
STAT_RX0 Meaning
0
0
DISABLED
: reception
transfers cannot be exe-
cuted.
STALL:
the endpoint is
stalled and all reception
requests
result
STALL handshake.
0
1
in
a
1
0
NAK
: the endpoint is na-
ked and all reception re-
quests result in a NAK
handshake.
VALID
: this endpoint is
enabled for reception.
1
1
7
0
1
DTOG
RX
STAT
RX1
STAT
RX0
0
0
0
0
STAT_RX1
STAT_RX0 Meaning
相關(guān)PDF資料
PDF描述
ST72T631K2M1 LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
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ST72T631K4B1 LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
ST72T631K4D0 LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
ST72631K1B0 LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
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