參數(shù)資料
型號: ST72T631K2M0
廠商: 意法半導體
英文描述: LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
中文描述: 低速USB 8高達16K的內存位微控制器系列,高達512字節(jié)RAM,8位ADC,水分散粒劑,定時器,SCI
文件頁數(shù): 78/109頁
文件大?。?/td> 857K
代理商: ST72T631K2M0
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I2C BUS INTERFACE
(Cont’d)
5.7.5 Low Power Modes
5.7.6 Interrupts
Figure 41. Event Flags and Interrupt Generation
The I2C interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC
register is reset (RIM instruction).
Mode
Description
No effect on I2C interface.
I2C interrupts exit from Wait mode.
I2C registers are frozen.
In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C
interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt
mode” capability.
WAIT
HALT
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
No
No
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
BTF
ADSEL
SB
AF
STOPF
ARLO
BERR
ITE
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
*
*
EVF can also be set by EV6 or an error from the SR2 register.
EVF
INTERRUPT
ITE
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