參數(shù)資料
型號: ST72T631K2M0
廠商: 意法半導(dǎo)體
英文描述: LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
中文描述: 低速USB 8高達(dá)16K的內(nèi)存位微控制器系列,高達(dá)512字節(jié)RAM,8位ADC,水分散粒劑,定時(shí)器,SCI
文件頁數(shù): 29/109頁
文件大小: 857K
代理商: ST72T631K2M0
ST7263
29/109
I/O PORTS
(Cont’d)
5.1.5 Port B
Table 11. Port B Description
Figure 20. Port B Configuration
PORT B
I/O
Alternate Function
Input*
Output
Signal
Condition
PB0
without pull-up
push-pull
Analog input (ADC)
CH[2:0] = 000 (ADCCSR)
PB1
without pull-up
push-pull
Analog input (ADC)
CH[2:0] = 001 (ADCCSR)
PB2
without pull-up
push-pull
Analog input (ADC)
CH[2:0]= 010 (ADCCSR)
PB3
without pull-up
push-pull
Analog input (ADC)
CH[2:0]= 011 (ADCCSR)
PB4
without pull-up
push-pull
Analog input (ADC)
CH[2:0]= 100 (ADCCSR)
IT5 Schmitt triggered input
IT4E = 1 (ITIFRE)
PB5
without pull-up
push-pull
Analog input (ADC)
CH[2:0]= 101 (ADCCSR)
IT6 Schmitt triggered input
IT5E = 1 (ITIFRE)
PB6
without pull-up
push-pull
Analog input (ADC)
CH[2:0]= 110 (ADCCSR)
IT7 Schmitt triggered input
IT6E = 1 (ITIFRE)
PB7
without pull-up
push-pull
Analog input (ADC)
CH[2:0]= 111 (ADCCSR)
IT8 Schmitt triggered input
IT7E = 1 (ITIFRE)
*Reset State
DR
DDR
LATCH
LATCH
DR SEL
DDR SEL
V
DD
PAD
ANALOG
SWITCH
ANALOG ENABLE
(ADC)
ALTERNATE ENABLE
ALTERNATE ENABLE
DIGITAL ENABLE
ALTERNATE ENABLE
ALTERNATE
OUTPUT
ALTERNATE INPUT
P-BUFFER
N-BUFFER
1
0
1
0
V
SS
D
C
V
DD
DIODES
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