參數(shù)資料
型號(hào)： SMJ34020AGB
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS SYSTEM PROCESSOR
中文描述： 圖形系統(tǒng)處理器
文件頁數(shù)： 88/92頁
文件大?。?/td> 1458K
代理商： SMJ34020AGB
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
88
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
video-interface timing: external sync inputs (see Note 10 and Figure 48)
NO.
’34020A-32
MIN
’34020A-40
MIN
UNIT
MAX
MAX
131
tsu(SL-VCKH)
tsu(SH-VCKH)
th(VCKH-SV)
Setup time, HSYNC, VSYNC, CSYNC low to VCLK no longer low
20
20
ns
132
Setup time, HSYNC, VSYNC, CSYNC high to VCLK no longer low
20
20
ns
133
Hold time, HSYNC, VSYNC, CSYNC valid after VCLK high
20
20
ns
NOTE 10: Setup and hold times on asynchronous inputs are required only to assure recognition at indicated clock edges.
See Note B
See Note A
D
C
B
A
HSYNC
VSVNC
CSYNC
(inputs)
VCLK
132
133
131
133
NOTES: A. If the falling edge of the sync signal occurs more than th(VCKH-SV) after VCLK edge A and at least tsu(SL-VCKH) before
edge B, the transition is detected at edge B instead of edge A.
B. If the rising edge of the sync signal occurs more than th(VCKH-SV) after VCLK edge C and at least tsu(SH-VCKH) before
edge D, the transition is detected at edge D instead of edge C.
Figure 48. Video-Interface Timing: External Sync Inputs
interrupt timing: LINT1 and LINT2 (see Figure 49)
NO.
’34020A-32
MIN
’34020A-40
MIN
UNIT
MAX
MAX
134
tsu(LINTL-CK2H)
Setup time, LINT1 or LINT2 low before LCLK2 no longer
low
tQ+45
tQ+40
ns
135
tw(LINTL)
Pulse duration, LINT1 or LINT2 low
8tQ
8tQ
ns
Although LINT1 and LINT2 can be asynchronous to the SMJ34020A, this setup ensures recognition of the interrupt on this clock edge.
This pulse duration minimum ensures that the interrupt is recognized by internal logic; however, the level must be maintained until it has been
acknowledged by the interrupt service routine.
LINT1
LINT2
LCLK2
LCLK1
135
134
Figure 49. Interrupt Timing: LINT1 and LINT2
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