參數(shù)資料
型號(hào)： SMJ34020AGB
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS SYSTEM PROCESSOR
中文描述： 圖形系統(tǒng)處理器
文件頁(yè)數(shù)： 26/92頁(yè)
文件大?。?/td> 1458K
代理商： SMJ34020AGB
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
During the address output to LAD by the SMJ34020A (Figure 4), the least significant four bits (LAD0–LAD3)
contain a bus-status code. PGMD low at the start of Q2 after RAS low indicates that this memory supports
page-mode operation. LRDY high at the start of Q2 after RAS low indicates that the cycle can continue without
inserting wait states.
DDOUT remains low after the initial address output on LAD (during Q4 after RAS goes low), indicating that a
memory write cycle is about to take place.
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