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| 型號： | SMJ34020AGB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁數(shù)： | 38/92頁 |
| 文件大小： | 1458K |
| 代理商： | SMJ34020AGB |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
As a special 1-megabit VRAM control cycle, the clock strech is also performed when the PMASKL and PMASKH
registers are set to nonzero values, CST in DPYCTL is cleared, VEN in CONFIG is set, and the byte-aligned
pixel-write instruction is executed (Figure 13). This cycle is indicated by CAS, TR/QE, and SF high and WE low
at the falling edge of RAS and by SF low at the falling edge of CAS. The data on LAD is written to memory just
as a normal DRAM write except that data in the write mask is used to enable DQs that are written to memory.
During the address portion of the cycle, the status on LAD0–LAD3
indicates that a pixel operation is being
performed (status code = 1101).
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Row
Address
Data Out 1
Q2
Q3
Q4
Q1
Data Out 2
1st Column
2nd Column
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
Q4
See clock stretch, page 20.
Figure 13. Write-Cycle Timing Using Mask
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