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參數(shù)資料
| 型號： | SMJ34020AGB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁數(shù)： | 41/92頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | SMJ34020AGB |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
This VRAM cycle shown in Figure 15 is performed when a video timeout occurs due to a match of the MLRNXT
register, VCE in DPYCTL is cleared, and SSV in DPYCTL is set. This cycle is indicated by TR/QE low and CAS,
SF, and WE high at the time RAS goes low. The timing of the low-to-high transition of TR/QE is not dependent
upon the timing of SCLK because there is not as great a timing constraint to position the cycle as in midline
reload. During the address portion of the cycle, the status on LAD0–LAD3 indicates a video-initiated VRAM
memory-to-register transfer (status code = 0100). Although PGMD and SIZE16 are ignored on this cycle, they
should be held at valid levels as shown.
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Row
Address
Tap Point
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
Q4
See clock stretch, page 20.
Figure 15. Memory-to-Split-Serial-Data-Register-Cycle Timing (VRAM Split-Register Read Transfer)
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