- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄373427 > SMJ34020AGB (Texas Instruments, Inc.) GRAPHICS SYSTEM PROCESSOR PDF資料下載
參數(shù)資料
| 型號(hào)： | SMJ34020AGB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁(yè)數(shù)： | 42/92頁(yè) |
| 文件大小： | 1458K |
| 代理商： | SMJ34020AGB |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)當(dāng)前第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
Figure 16 shows the VRAM cycle performed when a horizontal blank reload is requested by the video-control
logic and VCE and SRE in DPYCTL are both set. This cycle is indicated by TR/QE, WE and SF low and CAS
high at the time RAS goes low. The SOE pin of the VRAMs is used to select between write transfer and
pseudo-write transfer cycles (SOE must be generated by logic external to the SMJ34020A). During the address
portion of the cycle, the status on LAD0–LAD3 indicates that a video-initiated VRAM register-to-memory
transfer (status code = 0100) is being performed. Although PGMD and SIZE16 are ignored on this cycle, they
should be held at valid levels as shown.
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Row
Address
Tap Point
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
Q4
See clock stretch, page 20.
Figure 16. Serial-Data-Register-to-Memory-Cycle Timing (VRAM-Write Transfer, Pseudo-Write Transfer)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SMJ34020AHT | GRAPHICS SYSTEM PROCESSOR |
| SMJ4256 | 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| SMJ4256FV | 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| SMJ4256JD | 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| SMJ44400 | 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ34020AGBM32 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR |
| SMJ34020AGBM40 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR |
| SMJ34020AHT | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR |
| SMJ34020AHTM32 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR |
| SMJ34020AHTM40 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。