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| 型號： | SMJ34020AGB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁數(shù)： | 59/92頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | SMJ34020AGB |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
59
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
Data transfer from a coprocessor to memory requires an initialization cycle to inform the coprocessor what is
to be transferred and then a memory cycle to perform the actual transfer (Figure 28). The coprocessor can place
status information on LAD during the initialization cycle for the SMJ34020A. The memory cycle includes a dead
cycle to enable the SMJ34020A to take LAD drivers to the high-impedance state before the coprocessor
activates its LAD bus drivers to the memory. Two types of memory-to-coprocessor instructions are supported.
Both provide a count (from 1 to 32) of data to be moved in the instruction. Both also specify a register to be used
as an index into memory. One uses this index register with a postincrement and the other uses it with a
predecrement after each transfer cycle.
LCLK1
LCLK2
CAMD
RCA
LAD
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LAD
Command
Q2
Q3
Q1
SF
DDIN
Data 1
LRDY
BUSFLT
Address
Data 2
2nd Column
1st Column
Row
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
(TMS34020A)
(see Note A)
(Coprocessor)
(see Note A)
Status
GI
ALTCH
RAS
CAS
WE
TR / QE
DDOUT
PGMD
SIZE16
(see Note B)
R0
R1
Command Cycle
Address
Data Transfer
Data Transfer
Spacer
Q4
See clock stretch, page 20.
NOTES: A. LAD (SMJ34020A):
LAD (coprocessor):
Command:
Address:
Data n:
Status:
B. All coprocessor cycles are implemented as 32-bit operations; therefore, SIZE16 should be high during these cycles.
Figure 28. Transfer-Coprocessor Register(s) to Memory (ALTCH High During Data Transfer)
Output to LAD by the SMJ34020A
Output to LAD by the coprocessor
Coprocessor ID, instruction and status code present on LAD
Memory address for the data transfer, with coprocessor status code
Data from the coprocessor (number of values transferred depends on a count in the instruction)
Optional coprocessor status register output to LAD bus
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