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| 型號： | SMJ34020AGB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁數(shù)： | 34/92頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | SMJ34020AGB |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
Clock stretch is a special 1-megabit VRAM control cycle that is executed when VEN in the CONFIG I/O register
is set and PMASKL and/or PMASKH are written (Figure 9). This cycle is indicated by CAS, WE, TR/QE, and
SF high at the falling edge of RAS and SF low at the falling edge of CAS. As the plane mask is copied to the
PMASK register(s), it is also output on LAD to be written to a special register on the VRAM that is used in
subsequent cycles requiring a write mask. During the address portion of the cycle, the status on LAD0–LAD3
indicates a write-mask load is being performed (status code = 0110). Although CAMD, PGMD, and SIZE16 are
ignored on this cycle, they should be held at valid levels as shown.
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q1
PMASK Row
PMASK Address
PMASK Data
Zero Address
Q2
Q3
Q4
Q1
Not PMASK Data
PMASK Column
All-Zero Address
Write to the PMASK I/O Register
Load-Write-Mask Cycle
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
Q4
Q4
See clock stretch, page 20.
Figure 9. Load-Write-Mask-Cycle Timing
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