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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
68
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
local-bus timing: output clocks (see Note 4 and Figure 34)
NO.
SMJ34020A-32
MIN
4tc(CKI)+ s
2tQ–15
2tQ–10
2tQ–15+ s
2tQ–10+ s
’34020A-40
MIN
4tc(CKI)+ s
2tQ–13.5
2tQ–7
2tQ–13.5+ s
2tQ–7+ s
UNIT
MAX
MAX
11
tc(LCK)
tw(LCKH)
tw(LCKH)
tw(LCKL)
tw(LCKL)
tt(LCK)
th(CK1H-CK2L)
th(CK2H-CK1H)
th(CK1L-CK2H)
th(CK2L-CK1L)
th(CK1H-CK2H)
th(CK2H-CK1L)
th(CK1L-CK2L)
th(CK2L-CK1H)
Cycle time, period of local clocks LCLK1, LCLK2
ns
12
Pulse duration, local clock high
ns
12a
Pulse duration, LCLK1 high (see Note 5)
ns
13
Pulse duration, local clock low
ns
13a
Pulse duration, LCLK1 low (see Note 5)
ns
14
Transition time, LCLK1 or LCLK2
15
13.5
ns
15
Hold time, LCLK2 low after LCLK1 high
tQ–15
tQ–15
tQ–15
tQ–15+ s
3tQ–15
3tQ–15+ s
3tQ–15+ s
3tQ–15+ s
tQ–13.5
tQ–13.5
tQ–13.5
tQ–13.5+ s
3tQ–13.5
3tQ–13.5+ s
3tQ–13.5+ s
3tQ–13.5+ s
ns
16
Hold time, LCLK1 high after LCLK2 high
ns
17
Hold time, LCLK2 high after LCLK1 low
ns
18
Hold time, LCLK1 low after LCLK2 low
ns
19
Hold time, LCLK2 high after LCLK1 high
ns
20
Hold time, LCLK1 low after LCLK2 high
ns
21
Hold time, LCLK2 low after LCLK1 low
ns
22
Hold time, LCLK1 high after LCLK2 low
ns
This is a functional minimum and is not tested. This parameter can also be specified as 4tQ.
NOTES:
4. s= tQ if using the clock stretch;
s= 0 otherwise
5. Parameters 12a and 13a are specified with 1.5 V timing levels (parameters 12 and 13 are specified with standard timing voltage
levels).
LCLK1
LCLK2
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
14
14
14
11
12
13
19
21
22
15
16
17
18
11
12
13
14
20
12a
13a
NOTE A: Although LCLK1 and LCLK2 are derived from CLKIN, no timing relationship between CLKIN and the local clocks is to be assumed,
except the period of the local clocks is four times the period of CLKIN.
Figure 34. Local-Bus Timing: Output Clocks