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| 型號(hào)： | SMJ34020AGB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁數(shù)： | 70/92頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | SMJ34020AGB |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
70
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
QW
QX
QY
QZ
tt(SG)
td(SG-SGV)
td(SGV-SG)
th(CK-SG)
td(CK-SGV)
th(CK-SG)
LCLKx
SIGNALa
SIGNALb
tw(SGH)
tw(SGL)
td(SGV-SG)
td(SG-SGV)
td(CK-SGV)
td(SGV-SG)
td(SG-SGV)
tt(SG)
See Note A
NOTE A: Any of these quarter phases could be 2tQ if they are stretched (see clock stretch,
page 20).
Figure 35. Output Signal Characteristics
example of how to use the general output signal characteristics
Assume a system is using a SMJ34020A-32. Determine the maximum time from the start of the falling edge
of ALTCH to the time when data must be valid on LAD for a local-memory write cycle.
From the local-memory read-modify-write-cycle timing diagram on page 28, the time from the falling edge of
ALTCH to valid data on LAD is roughly Q3 + Q4; i.e., 2t
Q
. A more precise value can be obtained by using the
table of output signal characteristics.
The parameter of interest is t
d(SG-SGV)
. Note that in Figure 35, there are two representations of t
d(SG-SGV)
that
relate SIGNALa and SIGNALb (the third representation of this parameter relates SIGNALb to itself and is not
useful in this example). Let SIGNALa represent ALTCH because ALTCH is making a transition first. Let
SIGNALb represent LAD. By definition, the signal becoming valid (SGV) determines whether the fast value or
the slow value from the table is used.
In this case, for parameter t
d(SG-SGV)
, SGV s LAD. LAD s n the slow group, so the maximum value for t
d(SG-SGV)
is n
Q
+ 22. The value for nis 2 from the analysis of the diagram on page 28. Thus, the maximum time from the
start of the falling edge of ALTCH to the time when data must be valid on LAD for a local-memory write cycle
is 2t
Q
+ 22 ns.
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