參數(shù)資料
型號： SMJ34020AGB
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS SYSTEM PROCESSOR
中文描述： 圖形系統(tǒng)處理器
文件頁數(shù)： 54/92頁
文件大?。?/td> 1458K
代理商： SMJ34020AGB
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Row
Column
1st Write Valid
Local-Memory Host Write Cycle
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Row
Column
1st Address
2nd Address
Local-Memory Host Prefetch
Valid
Previous Read
HA/HBS
HCS
HREAD
HWRITE
HOE
HDST
LAD
GI
CAMD
RCA
SF
ALTCH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
DATA
(out)
DATA
(in)
Q4
Q4
(see HRDY
See clock stretch, page 20.
NOTE A: HRDY goes high at the start of Q2; however, the memory cycle writing data to memory is not completed
until the start of Q4 when ALTCH, CAS, and HOE return high. The host must not strobe new data into
the external latch until just after the start of Q4.
Figure 23. Host-Write Cycle Back-to-Back With Prefetch of Next Word and Implicit Addressing; HREAD
and HWRITE Used as Strobes
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