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參數(shù)資料
| 型號： | SiI3124ACBHU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI-X to Serial ATA Controller |
| 中文描述： | PCI - X到串行ATA控制器 |
| 文件頁數(shù)： | 62/88頁 |
| 文件大?。?/td> | 621K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
Bit [24]
: 3Gb/s Capable (R). This bit indicates whether the device is configured and tested for 3Gb/s (S-ATA
generation 2) operation. A zero indicates 1.5Gb/s operation. A one indicates 3Gb/s operation.
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
62
Bit [20:17]
: REQ64, DEVSEL, STOP, TRDY (R). These bits report the latched status of the corresponding PCI bus
signals that are latched at the rising edge of PCI RST# (when FRAME# and IRDY# are deasserted). Latched REQ64
indicates whether the PCI bus is 32 bits or 64 bits. Latched DEVSEL, STOP, and TRDY are decoded as shown in
the following table.
DEVSEL
STOP
TRDY
Mode
PCI, M66EN Off
PCI, M66EN On
PCI-X
PCI-X
PCI-X
PCI-X
Min Clock
0
33
50
66
100
Reserved
Max Clock
33
66
66
100
133
Reserved
Off
Off
Off
Off
Off
Off
On
Off
On
On
-
On
Off
On
-
Table 7-3 PCI bus Mode
Bit [16]
: M66EN (R). This bit reports the status of the M66EN PCI bus signal that indicates whether the PCI clock is
33 MHz (or less) or up to 66 MHz as shown in the preceding table.
Bit [3:0]
: Port Interrupt Enable (R/W). These bits, when set to one, allow assertion of an interrupt when the
corresponding port asserts an interrupt. When set to zero, the corresponding port interrupts are masked.
7.2.3 Global Interrupt Status
Address Offset: 44
H
Access Type: Read/Write 1 Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
R
I
Reserved
P
P
P
P
This register is used to determine the status of various chip functions.
Bit [31:30]
: Reserved (R). This bit field is reserved and returns zeroes when read.
Bit [29]
: I2C Interrupt (R/W1C). This bit indicates that the I2C Interrupt is pending. Writing a 1 to this bit clears the
interrupt.
Bit [28:4]
: Reserved (R). This bit field is reserved and returns zeroes when read.
Bit [3:0]
: Port Interrupt Status (R/W1C). These bits, when set to one, indicate that the corresponding port has an
interrupt condition pending. Writing a 1 to any of these bits clears the corresponding Command Completion Interrupt
Status, but not other interrupt sources.
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相關(guān)代理商/技術(shù)參數(shù) |
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| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
| SII3512 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3512ECTU128 | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 128-Pin TQFP 制造商:Silicone Image 功能描述: |
| SII3531 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
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