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參數(shù)資料
| 型號： | SiI3124ACBHU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI-X to Serial ATA Controller |
| 中文描述： | PCI - X到串行ATA控制器 |
| 文件頁數(shù)： | 58/88頁 |
| 文件大?。?/td> | 621K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
7.1.14 Header Write Enable
Address Offset: 48
H
Access Type: Read/Write
Reset Value: 0x0000_0000
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
58
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
H
This register contains the Hdr Wr Ena bit (in bit 0) used to enable writing to registers defined as read-only by the PCI
specification. This bit is required to meet PCI compliance testing that expects certain registers to be read-only. This bit is set
to enable write access to the following registers in the PCI Configuration Header: Device ID (03-02
H
), PCI Class Code (09-
0B
H
), Subsystem Vendor ID (2D-2C
H
), and Subsystem ID (2F-2E
H
).
7.1.15 MSI Capability
Address Offset: 54
H
Access Type: Read/Write
Reset Value: 0x0080_0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
6
Multiple
Message
Enable
Multiple
Message
Capable
M
Next Capability Pointer
Capability ID
This register defines the MSI Capability Message Control. The register bits are defined below.
Bit [31:24]
: Reserved (R) – This bit field is reserved and returns zeros on a read.
Bit [23]
: 64-bit Addr (R) – 64-bit Address Capable. This bit is hardwired to 1.
Bit [22:20]
: Multiple Message Enable (R/W) – This bit field defaults to 000
B
.
Bit [19:17]
: Multiple Message Capable (R/W) – This bit field defaults to 000
B
.
Bit [16]
: MSI Enable (R/W) – This bit is set to enable Message Signaled Interrupts.
Bit [15:08]
: Next Capability Pointer (R) –Next Capability Pointer. This bit field is hardwired to 00
H
; this is the last
Capability.
Bit [07:00]
: Capability ID (R) – This bit field is hardwired to 05
H
to indicate that this is a MSI Capability.
7.1.16 Message Address
Address Offset: 58
H
-5F
H
Access Type: Read/Write
Reset Value: 0x0000_0000_0000_0000
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Message Address Upper
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Message Address
00
This register specifies the memory address for an MSI memory write transaction. The memory address must be of a Dword
(bits 1:0 must be 0).
相關PDF資料 |
PDF描述 |
|---|---|
| SII3132 | PCI Express to 2-Port Serial ATA II Host Controller |
| SII3512 | PCI to Serial ATA Controller |
| SiI3512ECTU128 | PCI to Serial ATA Controller |
| SII3531A | PCI Express to Serial ATA Controller |
| SiI3531ACNU | PCI Express to Serial ATA Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
| SII3512 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3512ECTU128 | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 128-Pin TQFP 制造商:Silicone Image 功能描述: |
| SII3531 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
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