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參數(shù)資料
| 型號： | SiI3124ACBHU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI-X to Serial ATA Controller |
| 中文描述： | PCI - X到串行ATA控制器 |
| 文件頁數(shù)： | 51/88頁 |
| 文件大?。?/td> | 621K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Silicon Image, Inc.
7.1.1 Device ID – Vendor ID
Address Offset: 00
H
Access Type: Read /Write
Reset Value: 0x3124_1095
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0160-C
51
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device ID
Vendor ID
This register defines the Device ID and Vendor ID associated with the SiI3124. The register bits are defined below.
Bit [31:16]
: Device ID (R/W) – Device ID. The value in this bit field is one of the following three:
the default value of 0x3124 to identify the device as a Silicon Image SiI3124.
the value loaded from an external memory device; if an external memory device – Flash or EEPROM – is
present with the correct signature, the Device ID is loaded from that device after reset. See section 6 on
page 44.
system programmed value; if bit 0 of the Configuration register (48
H
) is set, the Device ID is system
programmable.
Bit [15:00]
: Vendor ID (R) – Vendor ID. This field defaults to 0x1095 to identify the vendor as Silicon Image.
7.1.2 PCI Status – PCI Command
Address Offset: 04
H
Access Type: Read/Write/Write-One-to-Clear
Reset Value: 0x02B0_0080 (PCI) / 0x0230_0080 (PCI-X)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
C
D
S
R
R
S
D
D
F
R
6
I
Reserved
I
F
S
A
P
V
M
S
B
M
I
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit 31
: Det Par Err (R/W1C) – Detected Parity Error. This bit set indicates that the SiI3124 detected a parity
error on the PCI bus (either address or data parity error) while responding as a PCI target.
Bit 30
: Sig Sys Err (R/W1C) – Signaled System Error. This bit set indicates that the SiI3124 signaled SERR on
the PCI bus.
Bit 29
: Rcvd M Abort (R/W1C) – Received Master Abort. This bit set indicates that the SiI3124 terminated a
PCI bus operation with a Master Abort.
Bit 28
: Rcvd T Abort (R/W1C) – Received Target Abort. This bit set indicates that the SiI3124 received a Target
Abort termination.
Bit 27
: Sig T Abort (R/W1C) – Signaled Target Abort. This bit set indicates that the SiI3124 terminated a PCI
bus operation with a Target Abort.
Bit [26:25]
: Devsel Timing (R) – Device Select Timing. This bit field indicates the DEVSEL timing supported by
the SiI3124. The hardwired value is 01
B
for Medium decode timing.
Bit 24
: Det M Par Err (R/W1C) – Detected Master Data Parity Error. This bit set indicates that the SiI3124, as
bus master, detected a parity error on the PCI bus. The parity error may be either reported by the target device
via PERR# on a write operation or by the SiI3124 on a read operation.
Bit 23
: Fast B-to-B Cap (R) – Fast Back-to-Back Capable. This bit is 1 in PCI Mode to indicate that the SiI3124
is Fast Back-to-Back capable as a PCI target. This bit is 0 in PCI-X Mode.
Bit 22
: Reserved (R) – This bit is reserved and returns zero on a read.
Bit 21
: 66 MHz Capable (R) – 66 MHz PCI Operation Capable. This bit is hardwired to 1 to indicate that the
SiI3124 is 66 MHz capable.
Bit 20
: Capabilities List (R) – PCI Capabilities List. This bit is hardwired to 1 to indicate that the SiI3124
implements Capabilities registers for Power Management, PCI-X, and Message Signaled Interrupt.
Bit [19]
: Interrupt Status (R).
Bit [18:11]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [10]
: Interrupt Disable (R/W).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII3132 | PCI Express to 2-Port Serial ATA II Host Controller |
| SII3512 | PCI to Serial ATA Controller |
| SiI3512ECTU128 | PCI to Serial ATA Controller |
| SII3531A | PCI Express to Serial ATA Controller |
| SiI3531ACNU | PCI Express to Serial ATA Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
| SII3512 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3512ECTU128 | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 128-Pin TQFP 制造商:Silicone Image 功能描述: |
| SII3531 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
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