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參數(shù)資料
| 型號： | SiI3124ACBHU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI-X to Serial ATA Controller |
| 中文描述： | PCI - X到串行ATA控制器 |
| 文件頁數(shù)： | 60/88頁 |
| 文件大?。?/td> | 621K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
60
Bit [31:24]
: PPM Data (R) – PCI Power Management Data. This bit field is hardwired to 0x19 to indicate a
power consumption of 2.5 Watt.
Bit [23:16]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [15]
:
PME Status (R) – PME Status. This bit is hardwired to 0. The SiI3124 does not support PME.
Bit [14:13]
:
PPM Data Scale (R) – PCI Power Management Data Scale. This bit field is hardwired to 01
B
to
indicate a scaling factor of 100 milliwatts.
Bit [12:09]
:
PPM Data Sel (R/W) – PCI Power Management Data Select. This bit field is set by the system to
indicate which data field is to be reported through the PPM Data bits (although current implementation hardwires
the PPM Data to indicate 2.5 Watt).
Bit [08]
:
PME Ena (R) – PME Enable. This bit is hardwired to 0. The SiI3124 does not support PME.
Bit [07:02]
:
Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]
:
PPM Power State (R/W) – PCI Power Management Power State. This bit field is set by the system
to dictate the current Power State: 00 = D0 (Normal Operation), 01 = D1, 10 = D2, and 11 = D3 (Hot).
7.2 Internal Register Space – Base Address 0
These registers are 32 or 64 bits wide and are the Global Registers of the SiI3124. Access to this register space is through
the PCI Memory space. In the following table a dashed line separates the register pairs that may be accessed as a 64-bit
register.
Address Offset
Register Name
00
H
04
H
08
H
0C
H
10
H
-3F
H
40
H
44
H
48
H
4C
H
-6F
H
50
H
54
H
58
H
70
H
74
H
78
H
7C
H
Port 0 Slot Status
Port 1 Slot Status
Port 2 Slot Status
Port 3 Slot Status
Reserved
Global Control
Global Interrupt Status
PHY Configuration
Reserved
BIST Control
BIST Pattern
BIST Status
Flash Address
GPIO
I
2
C Address
Flash Data
I
2
C Control
Reserved
I
2
C Data
Table 7-2 SiI3124 Internal Register Space – Base Address 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII3132 | PCI Express to 2-Port Serial ATA II Host Controller |
| SII3512 | PCI to Serial ATA Controller |
| SiI3512ECTU128 | PCI to Serial ATA Controller |
| SII3531A | PCI Express to Serial ATA Controller |
| SiI3531ACNU | PCI Express to Serial ATA Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
| SII3512 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3512ECTU128 | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 128-Pin TQFP 制造商:Silicone Image 功能描述: |
| SII3531 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
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